How to get to design closure faster with place-and-route for advanced nodes
The size and complexity of integrated circuit (IC) designs continues to grow with every technology node. Consequently, design closure time can become prolonged and uncertain. Designers can get faster and more predictable design closure in the implementation stage by using the right place-and-route software.
Place-and-route involves placing the circuitry elements and wiring them to get the best performance, power and area (PPA). With the complexity of modern IC designs, accomplishing this is not simple and linear; it typically requires multiple iterations. Physical implementation today goes beyond traditional placing and routing—it must account for wire and via resistance, IR drop, power specs, DRC specs, and a multitude of designs constraints beyond the timing constraints, which continue to push for faster performance. Reducing iterations saves engineers’ time and design costs and ensures the project will complete on time.
Challenges of place-and-route software
A big challenge today with electronic design automation (EDA) tools is their outdated, fragmented architecture that require multiple engines and data models. Because each step is in its own silo, additional time for communication and translation of the data is necessary between steps and delaying design closure. Without a common data model, each step of the flow is acting without the full design picture, which is not only inefficient but can lead to inaccurate results and bad correlation.
This traditional architecture (Figure 1) is difficult to use and support. The quality of results (QoR) is unpredictable. Every project needs its own individual design flow, which is time-consuming and does not allow for re-use. The semiconductor industry will benefit from a shift to a unified, detail-route-centric architecture, which can make QoR more predictable and alleviate design closure challenges.
How Aprisa place-and-route improves design closure
Route effects must be considered earlier in the design flow, during the placement stage. A detail-route-centric architecture built on a true unified data model (which goes beyond a unified database) enables more efficient and frequent communication between all engines in the tool, including placement optimization, CTS optimization, timing optimization, routing optimization, etc.
Aprisa place-and-route software was designed to provide up-to-date data in real-time between all common service engines. Every step of the flow is aware of and can react to the effects of routing on the design, including routing topology, length, layer and parasitics of wires and vias. This leads to improved quality of results (QoR), fewer design iterations within physical implementation and excellent correlations with signoff tools to minimize ECOs and achieve faster design closure.
Aprisa place-and-route software has patented features that lead to a shorter and more predictable time design closure. Aprisa’s detail-route-centric architecture coupled with its sign-off quality built-in timer produce tapeout-ready results, near zero DRCs at signoff, and a minimal number of ECOs due to its tight correlation with signoff timers.
In addition, its patented In-Hierarchy-Optimization (iHO) provides top-level timing closure without black box models or block flattening. With iHO designers can fix boundary paths at the top level and block level simultaneously, so there is no need for timing re-budgeting, generating ECOs, or abstraction models. iHO preserves your design hierarchy and can shorten top level design closure from weeks to days.
Want to learn more?
With Aprisa place-and-route software, design metrics are consistent throughout the place-and-route flow, which reduces iterations to achieve faster design closure. Watch the webinar to learn more about this technology and how its patented features and ease of use can help you on your next tapeout.
For more information on Aprisa place-and-route technology, visit the webpage to learn more.
