Hailo pushes utilization boundaries during physical implementation
As a young company with experienced physical designers in AI processors, Hailo set out to transform the AI chip industry by developing the best performing AI processors for edge devices without the need for an external memory. These ultra-low-power processors are efficient and compact enough to compute and interpret vast amounts of data in real time. They can be embedded in edge devices directly for use in automotive, retail, and other industries.
Hailo envisioned implementing their design with the following criteria:
- The smallest possible area, which translates to low cost and normally to lower IR drop
- The lowest dynamic power
- The ability to support a non-conforming floorplan
To achieve such criteria, Hailo looked to Aprisa, the digital implementation solution from Siemens Digital Industries Software. They share their experience in an on-demand webinar “Hailo achieves unprecedented AI performance using Aprisa digital implementation flow.”
Working with Siemens, the engineers at Hailo felt confident that they could rely on Aprisa to meet the strict requirements of their design because of Aprisa’s flexibility and features. They also knew that they had a dependable partner in Siemens, so when they needed to fine tune Aprisa to achieve their goals, they would get the answers and enhancements requested without sacrificing their time-to-market.
Hailo’s design implemented in Aprisa had a non-conforming floorplan with many srams throughout, rendering it unfriendly for routing and adding buffers, two of the most critical aspects for meeting high-performance goals. In addition, the design targeted a very aggressive utilization of 90%, which inherently poses challenges in placement, routing and IR drop complexity.
“When we compared Aprisa on our Hailo blocks against the third-party competitor’s tool, Aprisa gave us the best area which led to the best IR drop results,” said Elyasaf Munk, Physical Design Engineer at Hailo Technologies. Aprisa was also able to route the un-friendly floorplan in a few cycles without compromising on dynamic power, which was an outcome very welcomed by Hailo.
Hailo was also impressed with the hold-aware useful-skew feature in Aprisa that helped to minimize the amount of delay buffers inserted when they were pulling the clock during the place stage to meet their setup timing. “I think this is one of the reasons for the very good area results that we got,” said Munk.
The backend designers found that Aprisa provided a very robust and easy to use ECO flow with a lot of flexibility, which helped them apply any last-minute changes coming from their signoff tools. Their overall tapeout experience was enhanced by the quick turn-around time from the Siemens support team to meet their strict and specialized metrics.
Aprisa delivers an easy and quick way to ramp up on new designs and offers a comprehensive out-of-the-box experience with reference flows that can be used for multiple projects. Additionally, Aprisa is very customizable and has great flexibility for designs that push the boundaries on different metrics. Aprisa is certified for advanced process nodes from the major foundries, including the TSMC N5/N4 processes and Samsung 4LPE. Aprisa is currently being used on Hailo’s tapeout designs.
