Automated full-chip ESD protection verification is here!
By Frank Feng – Mentor, A Siemens Business
Full-chip ESD verification can be challenging, especially at advanced nodes. Adopting logic-driven, context-aware ESD checking can ensure your designs are robustly and consistently protected against operational failure.
Electrostatic discharge (ESD) is one of oldest reliability issues in integrated circuit (IC) design. So you’d think that, by now, we’d have all the wrinkles ironed out of ESD protection verification. And for the most part, you’d be right…until it comes to full-chip verification. Verifying that a chip with multiple IO/power/ground ports is protected from the full range of potential ESD events is still a formidable task in most advanced node chip design projects.
Most design companies still use manual inspection by an ESD engineer. But when you’re at the chip assembly stage, that takes up precious time in the schedule. And if you happen to overlook anything? You could end up having to delay the tapeout, or worse, the product goes to market and fails. Ouch…
So what’s the big obstacle to chip-level ESD verification? You have to take into account circuit connectivity in conjunction with the correlated geometrical and electrical data across the entire layout. Dedicated physical and circuit verification tools aren’t designed to comingle polygons and voltages, and dynamic simulation isn’t feasible at the full-chip level.
Fortunately, now there’s another option. With the Calibre® PERC™ reliability platform, you get an automated rule-based (static) and context-aware approach that can perform the two primary functions of full-chip ESD protection verification:
- Verifying the existence of ESD protection circuits
- Verifying the robustness of ESD current path interconnect
Automated context-aware chip-level ESD protection verification can not only reduce your time to tapeout, but also ensure that your designs are robustly and consistently protected against operational failure due to ESD events.
Want to learn more? Download a copy of our white paper, Logic-driven layout: Enabling context-aware full-chip ESD verification, to get started!
