Interactive symmetry checking for analog/custom ICs: Faster, easier, more accurate
By Sara Khalaf
While the reliability and performance of multiple types of designs such as analog, MEMs, and image sensors depend on many factors, one critical factor is device matching, which in turn is primarily dependent on the symmetry of the circuit layout.
As technology nodes advance, traditional methods that designers have depended on to validate design symmetry are simply not cutting it anymore. Most designers have ways to construct their designs in a symmetric manner, so sometimes they depend on the idea that their design will be correct by construction, and they don’t do any type of checking to validate that their design is actually symmetrical. Unfortunately, this method is risky because it doesn’t take into consideration errors due to placement issues or errors due to the context.
Some designers visually inspect their designs, or perform manual measurements to validate the symmetry of their design, while others invoke a parasitic extraction run and compare the values in the netlist. Yet others write their own complex rule checks to validate design symmetry. While all of these methods CAN work, they are not typically practical or quick solutions.
What IS practical, and fast, and accurate, is an interactive method for validating symmetry while the designer is designing the layout inside the design environment, without the need to write a rule deck. With interactive symmetry checks, designers can validate a design at any point. They don’t need to completely finish the design to run a rule deck, or to perform a parasitic extraction run. Error markers that point to the exact location of the errors enhance and speed up the process of implementing the appropriate fix.
This interactive symmetry approach is available now in the Calibre nmPlatform. And, because this solution is enabled through the Calibre RealTime platform, designers can upload a Calibre sign-off DRC rule deck to run in parallel with Calibre symmetry checking, ensuring that fixes they implement are DRC-clean. Error markers provide precise error locations, as well as information about the error itself, to enable designers to quickly debug the cause and determine the optimum fix. Both 1D and 2D symmetry checks are supported, allowing designers to accurately and efficiently resolve all symmetry violations while ensuring a DRC-clean layout.
Want to learn more about interactive symmetry checking? Download a copy of our paper, Interactive symmetry checking provides faster, easier symmetry verification for analog and custom IC designs.
