By Carey Robertson and Khaled AbouZeid, Mentor Graphics Designers incorporating MEMS devices into high-volume CMOS ICs need new processes, data,…
By Jeff Wilson, Mentor Graphics With manufacturing innovations and new DFM solutions, CMP modeling is gaining renewed popularity
By John Ferguson, Mentor Graphics Like PDKs for ICs, qualified assembly design kits for packages can ensure the quality and…
By Mohamed ElRefaee, Mentor Graphics Accurate parasitic extraction of touchscreens is essential for ensuring the high-quality performance the market demands
By Dina Medhat, Mentor Graphics Automated voltage propagation provides an accurate way to detect and correct those hard-to-find EOS conditions…
David Abercrombie continues his expert advice to P&R and chip finishing engineers on understanding and debugging multi-patterning errors accurately and…
By David Abercrombie, Mentor Graphics Multi-patterning errors in P&R layouts can be intricate, and their solutions may not be obvious
By Matthew Hogan, Mentor Graphics Reliability issues have gone way beyond DRC and LVS verification…
By Jeff Wilson, Mentor Graphics At 20nm, new fill constraints drive up the time and complexity of the fill process….
