PERC

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What’s an ESD design window, and why do I care?

October 6, 2022

By Derong Yan As we move to advanced semiconductor process nodes, electrostatic discharge (ESD) issues have become more critical in…

By Design With Calibre
2 MIN READ

A touchy subject: RF IC layout verification

May 24, 2022

By Neel Natekar Radio frequency (RF) circuitry is an essential component of many of the critical applications we now rely…

By Design With Calibre
2 MIN READ

DRC voltage text annotations: Manually placed texts can be wrong!

March 14, 2022

By Abdellah Bakhali System-on-chip (SoC) designs often use multiple intellectual property (IP) blocks from multiple IP providers. Each IP provider…

By Design With Calibre
2 MIN READ

Do you trust the reliability of your 2.5D/3D IC package designs?

March 9, 2022

By Dina Medhat 2.5D/3D ICs have become an innovative solution for many design and integration challenges. Basic physical verification for…

By Design With Calibre
3 MIN READ

Reliability checking for memory circuit design doesn’t have to destroy your eyesight!

March 7, 2022

By Hossam Sarhan Memory blocks contain sensitive analog circuits that are crucial for the proper functionality of the whole design….

By Design With Calibre
< 1 MIN READ

Is there a quick and easy way to calculate P2P resistance or current density between any two coordinates in my IC design layout?

February 28, 2022

By Li Li Why, yes, there is! As you know, Calibre® PERC™ logic-driven layout (LDL) current density (CD) and point-to-point…

By Design With Calibre
< 1 MIN READ

Stronger together! Context-aware SPICE simulation combines the strengths of static and dynamic verification for faster, more precise full-chip ESD verification

January 31, 2022

By Neel Natekar Running dynamic simulations for full-chip ESD verification of ICs has become increasingly difficult (and in some cases,…

By Design With Calibre
2 MIN READ

Cloud Computing Makes Overnight TAT Attainable

October 11, 2021

By Matthew Hogan and Derong Yan As we all know, during the final sign-off verifications of full chip system-on-chip (SoC)…

By Design With Calibre
3 MIN READ

Caution! Avoid detours when improving resistance on ESD paths

August 19, 2021

By Derong Yan As overall transistor dimensions shrink, integrated circuit (IC) chip designs become more sensitive to the damage caused…

By Design With Calibre
2 MIN READ