Design with Calibre

The industry-leading Calibre toolsuite provides physical verification (DRC), circuit verification (LVS, PEX), and reliability verification (PERC), as well as Calibre DFM optimization, to ensure IC designs will deliver the power, performance, and foundry yield today’s markets demand. Across all process nodes and design styles, innovative functionality ensures the Calibre toolsuite provides accurate, efficient, comprehensive IC verification while minimizing resources and tapeout schedules.

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DRC voltage text annotations: Manually placed texts can be wrong!

March 14, 2022

By Abdellah Bakhali System-on-chip (SoC) designs often use multiple intellectual property (IP) blocks from multiple IP providers. Each IP provider…

By Design With Calibre
2 MIN READ

Do you trust the reliability of your 2.5D/3D IC package designs?

March 9, 2022

By Dina Medhat 2.5D/3D ICs have become an innovative solution for many design and integration challenges. Basic physical verification for…

By Design With Calibre
3 MIN READ

Reliability checking for memory circuit design doesn’t have to destroy your eyesight!

March 7, 2022

By Hossam Sarhan Memory blocks contain sensitive analog circuits that are crucial for the proper functionality of the whole design….

By Design With Calibre
< 1 MIN READ

DAC in December?? A Review of Calibre Design Solutions at DAC 2021

March 3, 2022

Did it feel a bit weird to be submitting research papers for DAC 2022 while packing to go to DAC…

By Design With Calibre
4 MIN READ

Is there a quick and easy way to calculate P2P resistance or current density between any two coordinates in my IC design layout?

February 28, 2022

By Li Li Why, yes, there is! As you know, Calibre® PERC™ logic-driven layout (LDL) current density (CD) and point-to-point…

By Design With Calibre
< 1 MIN READ

The “next” technology node: ready or not, here it comes

February 22, 2022

By Shelly Stalnaker For years, decades even, the semiconductor industry has lived by the process node, which was originally named…

By Design With Calibre
2 MIN READ

Physical design engineers…Learn the secret to generating signoff fill in P&R and accelerating your tapeouts

February 21, 2022

By Srinivas Velivala Place and route (P&R) engineers are always on the lookout for ways to optimize their design flows…

By Design With Calibre
2 MIN READ

IC package designers—looking for multi-die, system-level signoff verification?

February 16, 2022

By Shelly Stalnaker Ever tried a food sample when you were shopping…not just because it’s free food (!), but because…

By Design With Calibre
2 MIN READ

Stronger together! Context-aware SPICE simulation combines the strengths of static and dynamic verification for faster, more precise full-chip ESD verification

January 31, 2022

By Neel Natekar Running dynamic simulations for full-chip ESD verification of ICs has become increasingly difficult (and in some cases,…

By Design With Calibre
2 MIN READ