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Track decomposition for SAMP processes—What you need to know

Track decomposition for SAMP processes—What you need to know

By David Abercrombie and Rehab Kotb-Ali – Mentor, A Siemens Business Understanding key requirements and root causes of errors is…

Open letter to the IC design community

Open letter to the IC design community

Joseph Sawicki – executive vice president, Mentor IC EDA Access free 30-Day On-Demand Training, plus webinars & knowledge content

More data is better in P2P debugging

More data is better in P2P debugging

By Slava Zuchenya – Mentor, A Siemens Business P2P debugging taking too much time? Using Calibre RVE colormapping can help…

Getting to tapeout faster… and easier!

Getting to tapeout faster… and easier!

By Sherif Hany – Mentor, A Siemens Business Complex reliability checks blowing your verification schedule? Learn how Calibre PERC smart…

Do you trust your AI/ML chips?

Do you trust your AI/ML chips?

By Neel Natekar – Mentor, A Siemens Business AI/ML chips are seeing growing adoption, but ensuring reliable operation and trusted…

Choosing a SAMP process at 5nm and below

Choosing a SAMP process at 5nm and below

By David Abercrombie, Rehab Kotb Ali, Ahmed Hamed-Fatehy – Mentor, A Siemens Business SADP, SAQP, and SALELE all have pros…

Partners help each other succeed…

Partners help each other succeed…

At their recent Open Innovation Platform (OIP) Ecosystem Forum held in Santa Clara, CA, TSMC named Mentor as their OIP…

MaxLinear and Calibre RealTime Digital in-design DRC: a winning combination

MaxLinear and Calibre RealTime Digital in-design DRC: a winning combination

By Srinivas Velivala – Mentor, A Siemens Business MaxLinear implemented the Calibre RealTime Digital interface for fast, iterative signoff DRC…

SRAM quality vs. flexibility: it’s a high-wire balancing act

SRAM quality vs. flexibility: it’s a high-wire balancing act

By Elven Huang – Mentor, A Siemens Business SRAM debugging at advanced nodes is challenging. With pattern matching and similarity…