Design with Calibre

The industry-leading Calibre toolsuite provides physical verification (DRC), circuit verification (LVS, PEX), and reliability verification (PERC), as well as Calibre DFM optimization, to ensure IC designs will deliver the power, performance, and foundry yield today’s markets demand. Across all process nodes and design styles, innovative functionality ensures the Calibre toolsuite provides accurate, efficient, comprehensive IC verification while minimizing resources and tapeout schedules.

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Electromigration and IC Reliability Risk

Electromigration and IC Reliability Risk

January 19, 2016

By Dina Medhat, Mentor Graphics Gradual damage from electromigration can affect product performance and reduce product lifetimes. Reliability analysis ensures…

By Design With Calibre
5 MIN READ
You’re Not Alone

You’re Not Alone

January 12, 2016

By Srinivas Velivala, Mentor Graphics Calibre How-To videos replace your roadblocks with fast solutions for tricky verification problems

By Design With Calibre
4 MIN READ
Resetting Expectations on Multi-Patterning Decomposition and Checking

Resetting Expectations on Multi-Patterning Decomposition and Checking

December 28, 2015

By David Abercrombie, Mentor Graphics Some common misconceptions about multi-patterning processes and just how they work.

By Design With Calibre
9 MIN READ
LEF/DEF IO Ring Check Automation

LEF/DEF IO Ring Check Automation

December 15, 2015

By Matthew Hogan, Mentor Graphics Designing today’s complex system-on-chips (SoCs) requires careful consideration when planning input/output (IO) pad rings…  

By Design With Calibre
5 MIN READ
Correct by Construction and Other Myths

Correct by Construction and Other Myths

December 8, 2015

By Joseph Davis, Mentor Graphics Is “correct by construction” a myth?

By Design With Calibre
5 MIN READ
Why Do We Need Assembly Design Kits for Packages?

Why Do We Need Assembly Design Kits for Packages?

December 1, 2015

By John Ferguson and Tarek Ramadan, Mentor Graphics Why do we need assembly design kits for IC packages?

By Design With Calibre
4 MIN READ
Design Rule Checking for Silicon Photonics

Design Rule Checking for Silicon Photonics

November 17, 2015

By Ruping Cao, Mentor Graphics Verifying silicon photonics designs requires new techniques, like equation-based DRC

By Design With Calibre
9 MIN READ
Reported Death of Moore’s Law Premature?

Reported Death of Moore’s Law Premature?

November 10, 2015

By Michael White, Mentor Graphics Is Moore’s Law dying? A look at the latest process node activity and technology

By Design With Calibre
5 MIN READ
Together At Last – Combining Netlist and Layout Data for Power-Aware Verification

Together At Last – Combining Netlist and Layout Data for Power-Aware Verification

November 3, 2015

By Beth Martin, with Sridhar Srinivasan, Yi-Ting Lee, and Frank Feng, Mentor Graphics Reliability checks on multiple-power-domain and mixed-signal designs…

By Design With Calibre
4 MIN READ