Design with Calibre

The industry-leading Calibre toolsuite provides physical verification (DRC), circuit verification (LVS, PEX), and reliability verification (PERC), as well as Calibre DFM optimization, to ensure IC designs will deliver the power, performance, and foundry yield today’s markets demand. Across all process nodes and design styles, innovative functionality ensures the Calibre toolsuite provides accurate, efficient, comprehensive IC verification while minimizing resources and tapeout schedules.

Latest posts

Automate those voltage-dependent DRC checks!

August 18, 2015

By Beth Martin with Dina Medhat, Mentor Graphics What do all these new voltage-dependent DRC rules mean, and how do…

By Design With Calibre

4 MIN READ

Video: ECO Fill Flow Framework

July 28, 2015

A video introduction to Mentor’s newly introduced utility called ecofill.

By Design With Calibre

< 1 MIN READ

Extraction Challenges Grow in Advanced Nanometer IC Design

July 21, 2015

By Carey Robertson, Mentor Graphics The Calibre xACT platform is a new type of extraction tool that provides a range…

By Design With Calibre

7 MIN READ

Automated Chip Polishing Can Make Your Design Shine

July 14, 2015

By Bill Graupp, Mentor Graphics A more robust design creates a more reliable product, and reduces yield variability over its…

By Design With Calibre

4 MIN READ

Are Three Eyes Better Than Two?

July 7, 2015

By David Abercrombie, Mentor Graphics Error analysis in triple patterning is challenging, but a pyramid approach helps designers prioritize and…

By Design With Calibre

11 MIN READ

Custom Layout Designers Need New Tools for New and Expanding Markets

July 1, 2015

By Srinivas Velivala, Mentor Graphics New debugging capabilities in Calibre RealTime can help shrink your time-to-tapeout while still ensuring high-quality…

By Design With Calibre

4 MIN READ

IoT, Cost-per-Transistor Extend Lifetimes of Established Technology Nodes

June 23, 2015

By Michael White, Mentor Graphics Much of the Internet of Things (IoT) functionality we crave is more cost-effective when implemented…

By Design With Calibre

6 MIN READ

How Close Can We Put Different Voltage Regions Together?

June 16, 2015

By Joe Davis, Mentor Graphics Calibre tools provide a complete flow for implementing, optimizing, and verifying voltage-dependent layouts against the…

By Design With Calibre

5 MIN READ

Parasitic Extraction of FinFET-based Memory Cells

June 11, 2015

By Karen Chow, Mentor Graphics Accurate and efficient FinFET characterization requires a parasitic extraction tool that can apply different extraction…

By Design With Calibre

6 MIN READ