Calibre IC manufacturing research for what comes next

By Germain Fenger Director of Product Management RET modeling, Calibre Semiconductor Manufacturing Solutions There is no rest in semiconductor manufacturing….

A new method of scaling and efficiency for the semi-manufacturing flow

By Beth Martin Calibre sets sail on Kubernetes While most Calibre semi-manufacturing jobs still run on on-premises compute clusters using…

Curves ahead for IC manufacturing

By John Sturtevant It turns out that the ideal mask pattern to print such a circle is in fact a…

ECO Fill Can Rescue Your SoC Tapeout Schedule

ECO Fill Can Rescue Your SoC Tapeout Schedule

By Vikas Gupta and Bhavani Prasad, Mentor Graphics Automated ECO fill helps you refill and re-verify late-stage changes quickly, while…

Will EUV Kill Multi-Patterning?

Will EUV Kill Multi-Patterning?

By David Abercrombie, Mentor Graphics Many people think EUV lithography means the end of multi-patterning. Do you?

Creating An Accurate FEOL CMP Model

Creating An Accurate FEOL CMP Model

By Ruben Ghulghazaryan, Jeff Wilson, and Ahmed AbouZeid FEOL CMP modeling helps designers and foundries predict CMP hotspots in advanced…

The Route to Faster Physical Verification and Better Designs

The Route to Faster Physical Verification and Better Designs

By Nancy Nguyen and Jean-Marie Brunet, Mentor Graphics Using the most accurate and up-to-date signoff engine instead of a limited…

A Look Behind the Mask of Multi-Patterning

A Look Behind the Mask of Multi-Patterning

By Michael White, Mentor Graphics An overview to the mystery of Multi-Patterning