By Dilan Heredia and Karen Chow Designing integrated circuits (ICs) for the 3 nm process node poses challenges never seen…
By Hossam Sarhan Work smarter, not harder. Isn’t that what everyone is always telling you? Of course, it’s excellent advice,…
By Karen Chow When Infineon needed to select a field solver for the development of their next-generation power semiconductor products,…
Did it feel a bit weird to be submitting research papers for DAC 2022 while packing to go to DAC…
By Matthew Hogan, Mentor Graphics Fast simulation and PEX are both crucial to interconnect robustness verification. Can your tools scale…
By Yousry Elmaghraby, Mentor Graphics Choosing the best PEX method for your full-chip or SoC design is essential. But how…
By Karen Chow, Mentor Graphics Signal integrity analysis at advanced nodes requires new and enhanced parasitic extraction techniques
By Mohamed ElRefaee, Mentor Graphics Accurate parasitic extraction of touchscreens is essential for ensuring the high-quality performance the market demands
By Carey Robertson, Mentor Graphics The Calibre xACT platform is a new type of extraction tool that provides a range…
