How AI-powered EDA solutions help design and verify library IP for SoCs
Note: If you’re interested in knowing more about the Solido Library IP Solution, check out our on-demand webinar about optimizing Library IP for high-performance, low power designs with Solido Library IP Solution, or read up on our related whitepaper.
One of the technology news highlights this week is a report (more of a confirmation) of heavy demand for AI-focused chips, including NVIDIA’s record revenue fueled by this. As AI-enabled technology rises towards mainstream usage both in consumer and commercial spaces, so do the SoCs and ICs that power those technologies.
As with all large, complex SoC designs, a key design component that impacts power, performance, and area metrics of the final product, are the standard cell and memory libraries used in the design.
Standard cells and memory bit cells are examples of highly replicated library components, production teams must ensure these components work across a broad range of process, voltage, and temperature (PVT) corners, and are robust enough to operate correctly to high yield when considering local variation. For example, for an SoC that has a yield target in the 3 to 4 sigma range, standard cells often require 6 sigma verification or higher, while operating correctly in low voltage conditions.
Just like standard cells, memory bit cells are impacted high sigma yield requirements due to extremely high instance counts within full memory instances. In addition, memory verification presents another unique challenge for many teams due to large full memory instance sizes.
At Siemens EDA, we’ve developed the Solido Library IP Solution to address these challenges. It’s an intelligent, AI powered solution, using differentiated Solido technologies to optimize power, performance, and area, for standard cell and memories, across library IP production stages such as design, verification, integration, and revisioning or retargeting.
Check out our whitepaper here. Or, head to our on-demand webinar!
