Addressing the Post-Layout Simulation Bottleneck for Analog Verification
Analog and mixed-signal designs are pervasive throughout the technology landscape today. The rapid growth in data expansion is driving an explosion in new designs and new requirements for high-performance computing, communications, automotive, and Internet of Things. This in turn is driving a push to smaller process geometries to address performance, size, and cost. This continued scaling of complex designs brings new opportunities, but also introduces new challenges to analog verification.
There are many benefits to migrating to smaller process geometries, such as an increase in the number of transistors that can fit into the same area, and the ability to balance the performance and power curve to match the needs of each application. However, these benefits can be easily negated by the increasing analog circuit sizes and complexity; and the exponential increase in interconnect resistance and distributed resistance and capacitance parasitics.
Because of this, simply simulating the schematic design without the inclusion of the layout effects introduces a huge risk, as it no longer represents an accurate analog model of the design and simplifying your design to speed up the verification process is not a viable option.
All of these contributing factors highlight that post-layout simulation is becoming the bottleneck for analog verification.
Interested in learning more about the latest Analog FastSPICE (AFS) innovative technology, designed to remove the post-layout simulation bottleneck? If yes, Siemens EDA is hosting a live web seminar on Wednesday, May 5th that you will want to attend.
