The term \u201cdebugging\u201d originated from an interesting incident in the 1940s when Admiral Grace Hopper, a US Navy scientist was working on a Mark II computer at Harvard University. Mark II used high-speed electromagnetic relays instead of the electro-mechanical counters used in the Mark I, making it much faster than its predecessor. One day the computer operation was disrupted, and when Grace\u2019s team traced the cause of the problem, they found an actual bug (a moth) that got stuck in one of the relays. When the insect (bug<\/strong><\/em>) was removed, the computer returned to its normal operation \u2013 whereupon she remarked that they \u201cde-bugged<\/em><\/strong>\u201d the system. On September 9, 1947, this moth was taped to the computer\u2019s logbook, with the note “first actual case of a bug being found<\/em>” \ud83d\ude0a<\/p>\n\n\n\n Fast forward to today, a recent Wilson Research Group study highlights where verification engineers are spending their time. They are involved in Test planning, Testbench development, Running simulation, and Debug. Out of all these tasks, debug is the most critical as it consumes more than 40% of their time.<\/p>\n\n\n\n Debug spans across all aspects of the semiconductor design and verification process, however of all the other classes, debugging a mixed-signal design is a tedious and time-consuming task. This is because debugging a mixed-signal design requires expertise from both the worlds \u2013 digital and analog.<\/p>\n\n\n\n For fast turnaround and to iron out preliminary bugs most verification engineers rely on higher abstraction in their verification methodology such as the use of real number model (RNM). This empowers the verification engineers to describe an analog block as a discrete floating-point model and enable it to simulate in a digital solver at near-digital simulation speeds. In a design, when an RNM block interacts with a standard logic block, signal conversion happens, and \u201creal to logic\u201d and \u201clogic to real\u201d boundary elements are inserted by the digital solver. The same is true in the case of a mixed-signal simulation when SPICE interacts with Logic or RNM blocks. The mixed-signal simulator inserts an \u201celectrical to real\u201d or \u201celectrical to logic\u201d boundary element. As the design hierarchy and complexity grow, the number of interactions increases, and it becomes cumbersome to debug these boundary conversions.<\/p>\n\n\n\n To learn more about mixed-signal debug methodologies, you can read our published article on semiengineering “Hug the Debug”<\/a> and to gain insights on what Siemens EDA has to offer to improve your mixed-signal debug productivity, watch our webinar “When it’s do or die – choose Debug<\/a>“. This webinar talks about Siemens EDA mixed-signal platform Symphony and Visualizer mixed-signal debug.<\/p>\n\n\n\n It is the first step to improve your verification productivity \u201cIf I had an hour to solve a problem, I’d…<\/p>\n","protected":false},"author":72118,"featured_media":218,"comment_status":"open","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"spanish_translation":"","french_translation":"","german_translation":"","italian_translation":"","polish_translation":"","japanese_translation":"","chinese_translation":"","footnotes":""},"categories":[1],"tags":[301],"industry":[],"product":[],"coauthors":[327],"class_list":["post-190","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-news","tag-mixed-signal-verification"],"featured_image_url":"https:\/\/blogs.stage.sw.siemens.com\/wp-content\/uploads\/sites\/58\/2021\/09\/Grace-Hopper-found-the-first-bug.jpeg","_links":{"self":[{"href":"https:\/\/blogs.stage.sw.siemens.com\/cicv\/wp-json\/wp\/v2\/posts\/190","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/blogs.stage.sw.siemens.com\/cicv\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/blogs.stage.sw.siemens.com\/cicv\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/blogs.stage.sw.siemens.com\/cicv\/wp-json\/wp\/v2\/users\/72118"}],"replies":[{"embeddable":true,"href":"https:\/\/blogs.stage.sw.siemens.com\/cicv\/wp-json\/wp\/v2\/comments?post=190"}],"version-history":[{"count":5,"href":"https:\/\/blogs.stage.sw.siemens.com\/cicv\/wp-json\/wp\/v2\/posts\/190\/revisions"}],"predecessor-version":[{"id":247,"href":"https:\/\/blogs.stage.sw.siemens.com\/cicv\/wp-json\/wp\/v2\/posts\/190\/revisions\/247"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/blogs.stage.sw.siemens.com\/cicv\/wp-json\/wp\/v2\/media\/218"}],"wp:attachment":[{"href":"https:\/\/blogs.stage.sw.siemens.com\/cicv\/wp-json\/wp\/v2\/media?parent=190"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/blogs.stage.sw.siemens.com\/cicv\/wp-json\/wp\/v2\/categories?post=190"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/blogs.stage.sw.siemens.com\/cicv\/wp-json\/wp\/v2\/tags?post=190"},{"taxonomy":"industry","embeddable":true,"href":"https:\/\/blogs.stage.sw.siemens.com\/cicv\/wp-json\/wp\/v2\/industry?post=190"},{"taxonomy":"product","embeddable":true,"href":"https:\/\/blogs.stage.sw.siemens.com\/cicv\/wp-json\/wp\/v2\/product?post=190"},{"taxonomy":"author","embeddable":true,"href":"https:\/\/blogs.stage.sw.siemens.com\/cicv\/wp-json\/wp\/v2\/coauthors?post=190"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}![\"\"](\"https:\/\/blogs.sw.siemens.com\/amsv\/wp-content\/uploads\/sites\/58\/2021\/09\/Wilson-Research-Group-Study-2020.png\")
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<\/a><\/figure>\n\n\n","protected":false},"excerpt":{"rendered":"