DDR – Increased Performance, Increased Design Challenges

If it weren’t for DDR SDRAM, many of today’s products would not be as feature-rich as they are, including servers, smartphones, computers, gaming consoles, and more. With each generation of DDR comes new advantages, such as increased speed and capacity and decreased power consumption, and also new challenges. Read our new white paper, The Design Advantages and Signal Integrity Challenges of DDR SDRAM.

DDR3 SDRAM brought improvements over DDR2, with bit rates that cover 800 Mb/s to 1600 Mb/s or more. It also increases bandwidth, lowers the operating voltage, and changes the driver impedance and on-die termination schemes. DDR3 uses “fly-by” topology, which means the Address/Command/Control and Clock are daisy-chained from one DRAM component to the next. This brings new signal-integrity design challenges, especially related to termination strategies, higher bit rates, and timing skew.

These complicated timing relationships can be difficult to analyze. To identify and resolve DDR device failures in general, or to resolve complicated timing relationships specifically, engineers need to conduct root-cause analysis which can be a tough and tedious task.

PADS HyperLynx DDR allows design engineers to simulate and analyze complex DDR circuits on their desktops to ensure an optimized product. To learn more, check out this video or request a free evaluation.

Jim