What causes undesirable SI in DDR designs?

What causes undesirable SI in DDR designs?

Continuing my blog series on DDR [Part 1 – Controlling DDR, Part 2 – Memory Bus Basics, Part 3 –…

3D Collision and Clearance Checking

3D Collision and Clearance Checking

In my last blog post, ECAD-MCAD co-design for First Pass Success, we reviewed how an efficient ECAD-MCAD co-design process can…

Should I Simulate Split Planes ?

Should I Simulate Split Planes ?

Almost all modern ICs require multiple supply voltages to operate, making power integrity one of the biggest problems in electronic…

Losing sleep over critical net routing and layout?

Losing sleep over critical net routing and layout?

High-speed memory interfaces and other sensitive connections multiply design complexity, forcing designers to meet tighter and tighter constraints on an…

PADS User2User meetings have begun!

PADS User2User meetings have begun!

I see it all the time – design engineers and designers who are way too busy to explore all the…

ECAD-MCAD Co-Design for First Pass Success

ECAD-MCAD Co-Design for First Pass Success

First pass success in the engineering domain is generally defined as the ability of a product to function as designed…

The Back and Forth of the DDR Data Bus

The Back and Forth of the DDR Data Bus

So far, this blog series has discussed the stress of DDR design and introduced the DDR memory and address busses. We…

Turn your dorm room into a makerspace!

Turn your dorm room into a makerspace!

What better way to go back to school than with a free, perpetual license of PADS® MakerPro design software! Digi-Key…

Understanding the DDR memory bus

Understanding the DDR memory bus

In the first blog in my series about DDR design, I talked about the stress of dealing with DDR. To…