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Tips for Deciphering DDR Simulation Results

Tips for Deciphering DDR Simulation Results

So you’ve finished your simulation, and you have the results. For a DDR bus, this involves gobs of information. But…

PCB Technology Leadership Award Winner: SIENNA ECAD

PCB Technology Leadership Award Winner: SIENNA ECAD

I’d like to congratulate the two Technology Leadership Award winners who used the PADS design flow on their boards. This…

A Brief Introduction to Schematic Integrity Analysis

A Brief Introduction to Schematic Integrity Analysis

Detect critical design errors and eliminate design respins caused by schematic errors by automating the process of board-level verification. Xpedition…

Tackling Next-Generation PCB Designs

Tackling Next-Generation PCB Designs

Tackle next-generation high-density analog, RF, and digital/mixed-signal designs with advanced tools for High-Speed and RF design. Take a look inside…

Tailor Your Approach to PCB Layout

Tailor Your Approach to PCB Layout

Why fumble around with a GUI that makes you search for settings and switches? Your time is valuable! With PADS…

DDR Design: Write leveling for better DQ timing

DDR Design: Write leveling for better DQ timing

So far, we’ve gone through the basics of the DDR Bus, and discussed some of the Signal Integrity and timing requirements of…

Are you meeting IC power demands for your design?

Are you meeting IC power demands for your design?

DC Drop Simulation is more than just being sure you have enough copper on the planes. You should also investigate…

Adding Automated EMC Analysis to PCB Layout

Adding Automated EMC Analysis to PCB Layout

Electromagnetic compatibility (EMC) compliance is a necessary condition for releasing products to market. National and international standards bodies define limits…

Receiver requirements in DDR design

Receiver requirements in DDR design

Once we have a topology for the data and address busses in mind or have them laid out on the…