{"id":1497,"date":"2014-05-05T10:25:12","date_gmt":"2014-05-05T17:25:12","guid":{"rendered":"https:\/\/blogs.mentor.com\/hyperblog\/?p=1497"},"modified":"2025-03-26T08:40:03","modified_gmt":"2025-03-26T12:40:03","slug":"does-trace-width-matter-much","status":"publish","type":"post","link":"https:\/\/blogs.stage.sw.siemens.com\/electronic-systems-design\/2014\/05\/05\/does-trace-width-matter-much\/","title":{"rendered":"Does trace width matter much?"},"content":{"rendered":"<p>I guess that all depends on what you are talking about&#8230; for Signal Integrity, trace width is very important, as it is one of the main factors in determining the characteristic impedance of a trace.\u00a0 For Power Integrity, trace width becomes important the longer your traces are.\u00a0 But in general, when you say &#8220;long traces&#8221; and &#8220;power integrity&#8221; in the same sentence,\u00a0you are\u00a0headed for some problems.\u00a0 A great way to figure out how bad your problems might be is to run some simulations &#8211; and that is where the PDN Editor in LineSim is an indispensable tool.\u00a0 You can modify things like trace width and see how much your DC voltage drop changes.\u00a0 You can also see the effect trace width will have on your decoupling capacitors.\u00a0 Earlier this year I blogged about <a href=\"http:\/\/www.pcdandf.com\/pcdesign\/index.php\/current-issue\/241-designer-s-notebook\/9233-designers-notebook-1401\" target=\"_blank\" rel=\"noopener noreferrer\">an article I wrote for PCD and F, where I explored some more common capacitor mounting methods and their effect on the PDN impedance<\/a>.\u00a0 I actually found that adjusting the spacing between the capacitor vias had a much more dramatic effect than the width of the traces connecting the capacitor to the vias.\u00a0 Obviously this is best achieved by using via-in-pad.\u00a0 But this effect can be further enhanced by using reverse-aspect-ratio capacitors, like 0204s.<br \/>\nSo, in this case, no, trace width did not matter much.\u00a0 But don&#8217;t take my word for it &#8211; experiment yourself using the <a href=\"http:\/\/www.mentor.com\/pcb\/product-eval\/hyperlynx-online-trial\" target=\"_blank\" rel=\"noopener noreferrer\">PI Virtual Lab<\/a>, available at:<br \/>\n<a href=\"http:\/\/www.mentor.com\/pcb\/product-eval\/hyperlynx-online-trial\" target=\"_blank\" rel=\"noopener noreferrer\">http:\/\/www.mentor.com\/pcb\/product-eval\/hyperlynx-online-trial<\/a><br \/>\nThere are a number of tutorials that walk through the process of analyzing power integrity on a PCB, and you can open up the LineSim PDN Editor and experiment with things like trace width, via spacing, number of vias, number of capacitors, capacitor values, stackup, plane spacing, and more to really quantify different design tradeoffs in designing a PCB power distribution network.<\/p>\n","protected":false},"excerpt":{"rendered":"<p>I guess that all depends on what you are talking about&#8230; for Signal Integrity, trace width is very important, as&#8230;<\/p>\n","protected":false},"author":71672,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"spanish_translation":"","french_translation":"","german_translation":"","italian_translation":"","polish_translation":"","japanese_translation":"","chinese_translation":"","footnotes":""},"categories":[13],"tags":[],"industry":[],"product":[],"coauthors":[],"class_list":["post-1497","post","type-post","status-publish","format-standard","hentry","category-news"],"_links":{"self":[{"href":"https:\/\/blogs.stage.sw.siemens.com\/electronic-systems-design\/wp-json\/wp\/v2\/posts\/1497","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/blogs.stage.sw.siemens.com\/electronic-systems-design\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/blogs.stage.sw.siemens.com\/electronic-systems-design\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/blogs.stage.sw.siemens.com\/electronic-systems-design\/wp-json\/wp\/v2\/users\/71672"}],"replies":[{"embeddable":true,"href":"https:\/\/blogs.stage.sw.siemens.com\/electronic-systems-design\/wp-json\/wp\/v2\/comments?post=1497"}],"version-history":[{"count":1,"href":"https:\/\/blogs.stage.sw.siemens.com\/electronic-systems-design\/wp-json\/wp\/v2\/posts\/1497\/revisions"}],"predecessor-version":[{"id":10235,"href":"https:\/\/blogs.stage.sw.siemens.com\/electronic-systems-design\/wp-json\/wp\/v2\/posts\/1497\/revisions\/10235"}],"wp:attachment":[{"href":"https:\/\/blogs.stage.sw.siemens.com\/electronic-systems-design\/wp-json\/wp\/v2\/media?parent=1497"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/blogs.stage.sw.siemens.com\/electronic-systems-design\/wp-json\/wp\/v2\/categories?post=1497"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/blogs.stage.sw.siemens.com\/electronic-systems-design\/wp-json\/wp\/v2\/tags?post=1497"},{"taxonomy":"industry","embeddable":true,"href":"https:\/\/blogs.stage.sw.siemens.com\/electronic-systems-design\/wp-json\/wp\/v2\/industry?post=1497"},{"taxonomy":"product","embeddable":true,"href":"https:\/\/blogs.stage.sw.siemens.com\/electronic-systems-design\/wp-json\/wp\/v2\/product?post=1497"},{"taxonomy":"author","embeddable":true,"href":"https:\/\/blogs.stage.sw.siemens.com\/electronic-systems-design\/wp-json\/wp\/v2\/coauthors?post=1497"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}