Thought Leadership

Surprise! DVCon 2021 has an AMS Track – See you there

February 26, 2021 • 2 MIN READ
By Sumit Vishwakarma

It is fascinating and often surprising to find the origin of words that we commonly use every day. For example, in the verification world, we have been hearing the word “Verilog” for several decades and we know that Verilog (IEEE 1364 std.), is a hardware description language (HDL) used to model electronic systems. However very few know that this word is a portmanteau of the words “verification” and “logic” [1]. I learned about this at DVCon 2019, the time when we used to have physical/live events.

The Design and Verification Conference (DVCon) is one of the premium conference covering the application of EDA tools, languages, and IPs for the design and verification of semiconductors ICs. It also provides a great opportunity to network with like-minded people such as design and verification engineers, IP integrators, and chip architects.

DVCon has several tracks with much focus on digital verification, however there is also an AMS track (surprised?) which focuses on Analog and Mixed Signal Verification tools and methodologies. We are excited to announce that this year, Siemens EDA is presenting a session in this track in partnership with Analog Value ltd. The title of the talk is:

A Novel Variation-Aware Mixed-Signal Verification Methodology to achieve High-Sigma Variation coverage at nanometer designs

Variation analysis is significantly important in modern nanometer process geometries especially for mission critical applications such as health, automotive and industrial. Traditional verification approaches to analyze statistical variations are time consuming and provides inadequate coverage. In this session we discuss a novel ‘variation aware mixed signal verification’ methodology that relies on designers knowledge and use of machine learning based EDA tools. This approach is applied for a Time-Domain 2-step ADC architecture which is used in automotive RADAR application and is fabricated with 22nm FDSOI Global Foundry process

Please join us at DVCon 2021 on March 3 at 10AM. And if you like our talk, do leave us a review on Yelp (jk), which by-the-way is a portmanteau of “Yellow Pages” + “help” 🙂

To find more: visit DVCon Agenda

Siemens EDA at DVCon
DVCon 2021 AMS Session presented by Siemens EDA & Analog Value Ltd.

[1] http://archive.computerhistory.org/resources/access/text/2013/11/102746653-05-01-acc.pdf

Sumit Vishwakarma

Sumit Vishwakarma has over 15 years of experience in the EDA industry including 10 years in AMS and 5 years in digital verification. At Mentor, Sumit is responsible for product management and marketing functions across Mentor’s AMS verification product portfolio driving circuit simulation, mixed-signal, and library characterization platform. Over the years, Sumit has held various roles ranging from design engineer, application engineer and verification specialist at Intel, Springsoft and Synopsys. Before joining Mentor, Sumit was responsible to drive the sales and development of Analog/Mixed-Signal simulators and verification and debug platforms at Synopsys. He has published papers in IEEE, DesingCon, DAC, SNUG, U2U, and multiple tech articles and blogs on mixed-signal verification methodologies. Sumit has an MS in Electrical engineering from Arizona State and Management Science & Engineering PD from Stanford. He is a vivid digital artist and loves teaching art to kids.

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This article first appeared on the Siemens Digital Industries Software blog at https://blogs.stage.sw.siemens.com/expertinsights/2021/02/26/surprise-dvcon-2021-has-an-ams-track-see-you-there/