Top 5 Articles of the Week
- Verification Flow: Panel Gauges Future Flows
- Auto Security and Technology Questions Persist
- Back-annotating DFM Enhancements to Place & Route Tools
- How Do You Solve a Problem Like Systems?
- Joint R&D Has Its Ups And Downs
Verification Flow: Panel Gauges Future Flows
EE Times
The DVCon India panel discussion “The Future Verification Flow” featured experts from Broadcom and Qualcomm and covered simulation, formal verification, emulation, and everything in-between.
Auto Security and Technology Questions Persist
Semiconductor Engineering 
Semiconductor automotive suppliers are taking more responsibility for ensuring safety and security of their ICs. Robert Bates, chief safety officer at Mentor Graphics, is featured in this expert roundtable.
Back-annotating DFM Enhancements to Place & Route Tools
EDN
Back-annotated DFM enhancements in place and route layout is critical for reducing manufacturing failures and improving yield. Mentor has developed utilities that make the back-annotation process simpler and faster. This article walks you through a demonstration of how the general process works.
How Do You Solve a Problem Like Systems?
Electronic Specifier
This article introduces a multi-board systems design solution for seamless multi-discipline collaboration.
Joint R&D Has Its Ups And Downs
Semiconductor Engineering
Joint R&D between academia and industry benefits both parties, but there are also drawbacks. Industry experts, including Greg Hinckley, offer their insights.
