EE Journal: Menta and Mentor Partner for High-Level Synthesis of Embedded FPGA IP

Excerpt from article: “Menta and Mentor Partner for High-Level Synthesis of Embedded FPGA IP“

Siemens EDA‘s Catapult™ HLS design tools provide an integrated development environment allowing designers to go from SystemC & C++ to eFPGA quickly and seamlessly while taking advantage of the fully customizable FPGA fabric provided by Menta. Menta’s IP is unique in allowing engineers to customize the eFPGA fabric to support the requirements of any application on any process node. Designers can specify the size and number of embedded logic blocks (eLBs), global clocks, memory, ALUs, and interfaces as required by any user application. SoCs that incorporate eFPGAs from Menta are ideal for emerging consumer, industrial, automotive and wireless applications, which require programmability for software and algorithm updates as standards evolve and change.

“Menta’s eFPGA IP offers a new level of configurability for SoCs, and Catapult HLS delivers a significantly reduced time to implementation compared to hand-coded RTL,” said Ellie Burns, director of marketing, Digital Design Implementation Solutions at Siemens EDA. “Together we can deliver a paradigm shift for SoC design that enables both a faster path from algorithm to optimized hardware and deliverable as a field upgrade to the SoC.”

Read the entire article on EE Journal originally published on April 2nd, 2019.