How MatchLib and SystemC Enables Early C-level Performance Analysis and Validation in an HLS Design Flow | Webinar
Learn how a High-Level Synthesis (HLS) design and verification flow built around Catapult HLS can dramatically speed up the design of an AI/ML hardware accelerator compared to a traditional RTL based flow. The webinar will focus on using the open-source MatchLib SystemC library, originally developed by NVIDIA, to perform rapid modeling and synthesis of an ML accelerator. It will demonstrate how the pre-HLS simulation, using MatchLib, can identify and fix potential system-level performance issues that are normally not found until much later in a hand-coded RTL design methodology. Finally we will present 2 customer case-studies from NVIDIA and Horizon Robotics, showcasing how these technologies work in conjunction to address our customers HLS design and verification challenges.
What you will Learn
- How to easily code SystemC designs for HLS using the MatchLib interface library.
- How MatchLib can be used to simulate the real hardware performance on the pre-hls model and expose potential performance bottlenecks before any RTL has been generated.
- How to use the code examples for your own purposes
Who Should Attend
- RTL Designers, System Architects, and Verification engineers interested in seeing how MatchLib and SystemC can improve design productivity in a High-Level Synthesis design flow
