Power: Front & Center of the Silicon Design Process
Power is one of the most critical design metrics today, but it still is an afterthought in far too many design flows. Traditional methods to optimize the design for power are concentrated at the backend of the design cycle, which is usually too late and too little, to make any significant difference. According to a survey conducted by Wilson Research in 2020, power is now the #3 reason for design re-spins, moving power to the front and center of the silicon design process. The greatest ability to impact power of a design is early in the design cycle – during the architecture and design phase.
The Design Methodology for Building Power Efficient RTL virtual seminar on April 12th, will present an effective hardware design methodology to build lowest power RTL IP and/or designs. It will highlight how early estimation of energy metrics and effective RTL optimization techniques can predictably deliver the best quality RTL optimized for power. The seminar will feature a combination of technical sessions and case studies delivered by industry leaders in low power chips – ARM and Cisco; sharing best practices that they adopted to build successful products.
A new automated input qualification methodology that Arm developed using PowerPro’s software portfolio that performs various data integrity checks at the IC design build and prototype stage in the following paper: Arm’s Input Qualification Methodology using PowerPro. This methodology ensures in quicker iterations that input data are high fidelity, leading to a well correlated power numbers. Should multiple iterations be necessary, a checkpoint database method is implemented to bypass the clean stages of the tool run so that further analysis is only required for areas with power violations – enabling fast iterative refinement.
Various checks pertaining to activity annotation (FSDB/SAIF/STW/QWAVE), technology libraries (.lib) and parasitic mapping (SPEF) are already a part of PowerPro. With PowerPro defining an input qualification methodology around these checks, much like Arm, users can save up to 88 percent of project time in achieving reliable power numbers.
