{"id":154,"date":"2019-12-30T16:12:00","date_gmt":"2019-12-30T21:12:00","guid":{"rendered":"https:\/\/blogs.sw.siemens.com\/hlsdesign-verification\/?p=154"},"modified":"2021-07-14T16:13:13","modified_gmt":"2021-07-14T20:13:13","slug":"semiengineering-improving-algorithms-with-high-level-synthesis","status":"publish","type":"post","link":"https:\/\/blogs.stage.sw.siemens.com\/hlsdesign-verification\/2019\/12\/30\/semiengineering-improving-algorithms-with-high-level-synthesis\/","title":{"rendered":"SemiEngineering: Improving Algorithms With High-Level Synthesis"},"content":{"rendered":"\n<p>Excerpt from article: \u201c<a href=\"https:\/\/semiengineering.com\/improving-algorithms-with-high-level-synthesis\/\" target=\"_blank\" rel=\"noreferrer noopener\">Improving Algorithms With High-Level Synthesis<\/a>\u201d<\/p>\n\n\n\n<blockquote class=\"wp-block-quote is-layout-flow wp-block-quote-is-layout-flow\"><p>Most computer algorithms today are developed in high-level languages on general-purpose computers. But someday they may be deployed in embedded systems where the development, verification, and validation of algorithms is done in languages like python, Java, C++, or even numerical frameworks like MatLab.<\/p><p>This is the goal of&nbsp;<a href=\"https:\/\/semiengineering.com\/knowledge_centers\/eda-design\/verification\/high-level-synthesis\/\" target=\"_blank\" rel=\"noreferrer noopener\">high-level synthesis<\/a>&nbsp;(HLS), and it aims to solve a fundamental problem in system design today. The basic idea is allowing hardware designers to build and verify hardware, with better control over optimization of the design architecture, describing the design at a higher level of&nbsp;<a href=\"https:\/\/semiengineering.com\/knowledge_centers\/eda-design\/models\/models-and-abstractions\/\" target=\"_blank\" rel=\"noreferrer noopener\">abstraction<\/a>&nbsp;while the tool implements the RTL. It also may be possible to use HLS to improve today\u2019s algorithms that run on that hardware.<\/p><p>The ultimate description will be in a hardware description language (HDL) at the&nbsp;<a href=\"https:\/\/semiengineering.com\/knowledge_centers\/eda-design\/definitions\/register-transfer-level\/\" target=\"_blank\" rel=\"noreferrer noopener\">register transfer level<\/a>&nbsp;(RTL). So it\u2019s not so much the algorithm that will be affected by HLS. It\u2019s the implementation of the algorithm.<\/p><p>\u201cHLS allows a large variety of architectures to be explored quickly, and enables very different implementations of an algorithm to be created without a lot of coding and without the risk of breaking the algorithm or requiring a lot of verification and debug,\u201d said Russell Klein, HLS platform program director at <a href=\"https:\/\/semiengineering.com\/entities\/mentor-a-siemens-business\/\" target=\"_blank\" rel=\"noreferrer noopener\">Siemens EDA.<\/a><\/p><\/blockquote>\n\n\n\n<p>Read the entire article on<a href=\"https:\/\/semiengineering.com\/improving-algorithms-with-high-level-synthesis\/\" target=\"_blank\" rel=\"noreferrer noopener\"> SemiEngineering<\/a> originally published on December 30th, 2019.<\/p>\n","protected":false},"excerpt":{"rendered":"<p>Excerpt from article: \u201cImproving Algorithms With High-Level Synthesis\u201d Most computer algorithms today are developed in high-level languages on general-purpose computers&#8230;.<\/p>\n","protected":false},"author":77876,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"spanish_translation":"","french_translation":"","german_translation":"","italian_translation":"","polish_translation":"","japanese_translation":"","chinese_translation":"","footnotes":""},"categories":[1,9],"tags":[301,356,380],"industry":[],"product":[84,176],"coauthors":[349],"class_list":["post-154","post","type-post","status-publish","format-standard","hentry","category-news","category-product-updates","tag-high-level-synthesis","tag-hls","tag-improving-algorithms","product-catapult","product-powerpro"],"_links":{"self":[{"href":"https:\/\/blogs.stage.sw.siemens.com\/hlsdesign-verification\/wp-json\/wp\/v2\/posts\/154","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/blogs.stage.sw.siemens.com\/hlsdesign-verification\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/blogs.stage.sw.siemens.com\/hlsdesign-verification\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/blogs.stage.sw.siemens.com\/hlsdesign-verification\/wp-json\/wp\/v2\/users\/77876"}],"replies":[{"embeddable":true,"href":"https:\/\/blogs.stage.sw.siemens.com\/hlsdesign-verification\/wp-json\/wp\/v2\/comments?post=154"}],"version-history":[{"count":2,"href":"https:\/\/blogs.stage.sw.siemens.com\/hlsdesign-verification\/wp-json\/wp\/v2\/posts\/154\/revisions"}],"predecessor-version":[{"id":156,"href":"https:\/\/blogs.stage.sw.siemens.com\/hlsdesign-verification\/wp-json\/wp\/v2\/posts\/154\/revisions\/156"}],"wp:attachment":[{"href":"https:\/\/blogs.stage.sw.siemens.com\/hlsdesign-verification\/wp-json\/wp\/v2\/media?parent=154"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/blogs.stage.sw.siemens.com\/hlsdesign-verification\/wp-json\/wp\/v2\/categories?post=154"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/blogs.stage.sw.siemens.com\/hlsdesign-verification\/wp-json\/wp\/v2\/tags?post=154"},{"taxonomy":"industry","embeddable":true,"href":"https:\/\/blogs.stage.sw.siemens.com\/hlsdesign-verification\/wp-json\/wp\/v2\/industry?post=154"},{"taxonomy":"product","embeddable":true,"href":"https:\/\/blogs.stage.sw.siemens.com\/hlsdesign-verification\/wp-json\/wp\/v2\/product?post=154"},{"taxonomy":"author","embeddable":true,"href":"https:\/\/blogs.stage.sw.siemens.com\/hlsdesign-verification\/wp-json\/wp\/v2\/coauthors?post=154"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}