The impact of 3d heterogeneous integration on semiconductor device reliability
So far in our 3D IC blog series, we’ve discussed front-end design approaches to develop 3D IC-based devices, the importance of early planning for interconnect verification and assembly level-layout vs schematic in 3D IC design verification. Today, we discuss the impact 3D IC has on semiconductor device reliability, ranging from understanding thermal interactions within and between semiconductor devices to the related thermo mechanical stress that can lead to warpage, cracking of micro bumps, hybrid bonds, and beyond. We will also look at electrical reliability from the aspects of latch-up, prevention, and ESD protection.
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Challenges 3D IC heterogeneous assemblies need to overcome to ensure reliability
Reliability has been challenging in the integrated circuit (IC) space but was manageable with design rule checking (DRC) rules. Now, it’s more challenging, and you can see situations where a die can be DRC-clean or LVS-clean but still fails on the manufacturing floor. What’s worse is when it works fine in the test bench but fails unexpectedly and prematurely once sold and used in the field. This failure risk leaves IC designers uncertain, particularly at the more advanced nodes.
Problems seen in the IC space are now starting to appear at a higher level from heterogeneous 3D IC environments. Unsurprisingly, these are formed by how devices and wires interact. That doesn’t change whether you’re connecting things within a chip or across multiple chips or chiplets. The problems are still there, particularly with larger electrostatic discharge (ESD) applications. Other cases include electrical overstress, especially if you’re targeting automotive or military-aerospace applications where reliability is critical. You don’t want to be on the road, and suddenly the car dies in the middle of traffic. Latch-up is a way to get two things inadvertently shorted together; they’re toggling together. Usually comes with a high voltage that enables it, something larger than expected, but those things can and do happen.
When we think of ESD, we think of a human finger, walking around scuffing your feet (especially as the weather gets colder), picking up a charge, and touching a chip somewhere that dissipates the charge into the chip and blows up the transistors. Yikes – that’s not a good thing and, unfortunately, not just a human discharge that can cause this. From chip manufacturing to its use in an application, there are many opportunities to cause an unexpected charge to appear and cause catastrophic events.
For system-on-chip (SoC) designs, we can find these situations. Even in the more complex scenarios, with tools like Calibre PERC, we can find them and apply known solutions to address them. In the case of latch-up, you need a good guard ring and a sufficient amount of taps and current ties. On the ESD side, it’s about ensuring you have adequate protection pads. With a sudden, unexpected charge, you can give it a fast path to ground instead of going through transistors.
The challenge in 3D IC design is that it differs from an SoC, where everything is in a single process and characterized all upfront. Designers connect things from multiple sources with slightly different behaviors, potentially from one die to the next. Design teams must make decisions to manage some of the differences. For an ESD issue that combines multiple dies, the designer must decide which die to place the fixes in or how to separate them across multiple dies. Another example is the size of the protection devices may change depending on the process of the individual chiplet. Many users already do this for SoC design. The challenge comes with scenarios where we don’t have to spend a lot of time thinking about them today but will need to – areas of thermal and stress.
3D heterogeneous integrations and thermal-related reliability issues
Design rules typically address thermal concerns for a single-process SoC. By following design rules, the design remains within relatively known performance and should behave. But as we introduce heat, we know the transistor is dependent on the operating temperature.
As the heat increases, electrons and the holes you’re trying to push through get heated, and that heat dissipates to the neighboring environment. To help minimize the impact, you move the heat around a little bit and, in the process, toggle a transistor. The faster you toggle that transistor or, the more current you try to push to make that happen, the hotter it will get.
With transistors that are close to each other, they typically start to heat up together. With SoC, design rules prevent those situations by not allowing transistors to be too close together and help designers avoid the dual-heating problem. With multi-die chiplets and heterogeneous processes, things are different, especially with floor planning.
For an SoC, floor planning involves identifying the plane and where to put the different components to get the behaviors with the optimal settings. For 3D IC, it’s not floor planning in the traditional sense because not everything is on the same floor, but the process uses many of the same concepts.
For example, you want to avoid having things that toggle fast and are frequently used next to similar items. Designers avoid putting a GPU and CPU close together because they get hot. With 3D designs, designers also avoid putting GPU on the CPU to prevent dissipating heat on the horizon plane and up and down in space.
When stacking dies on a traditional SoC, the transistors are on the silicon plane, and there’s a clear path for how temperature and heat are dissipated – it goes through the substrate. When multiple thin dies are stacked up, there could be a hot temperature in one that may have no place to go. In particular, the heat will move downward for face-to-face bonded copper-bonded dies with a top tier with a silicone component. The heat has no other place to go but to the transistors that are on the die that’s below it. With a longer path to an actual thermal escape, such as a thermal heat sink, the temperatures are hot and stay hot longer.
With all of these new variables, there are a lot of new considerations for 3D IC designs. Mitigating factors such as TSV through silicone to dissipate heat faster or a through insulator via to serve as a chimney to centralize heat take up space and introduce stresses. Temperature is going to impact how electrical behaviors present. The big challenge is figuring this out can only be done with collaboration.
3D IC designers need to understand a whole system from a multi-physics perspective to understand the behavior as the design evolves. It’s not typically known upfront what’s the best way to design a 3D IC – there are many, many more options on how to build a design with all the new dimensions. On the flip side, you now have many more opportunities for your particular design needs, and it’s more work to evaluate the appropriate options than it used to be.
Thermally-induced mechanical stress and 3D IC design reliability
Mechanical and physical stress – such as when you put a heavy piece of concrete on what you thought would be a straight board, the board bends right or maybe breaks. Stress and temperature are interrelated, but sometimes it’s easy to forget.
Considering the basics, look at the old ideal gas law: PV=nRT. Pressure, volume, and temperature are all interrelated. We’re not necessarily talking about a gas, but as a basic concept, stress increases as temperature increases. As temperatures come down, stresses go down, and vice versa — assuming volume is held constant. With an increase in stress on the transistor, it will behave differently.
For traditional SoC in the LVS space, we look into the post-layout simulation space to identify each transistor in context to evaluate the stressors. We capture the stressors as properties on the transistors that we feed into the transistor model for electrical analysis. Temperature creates stress, and stress creates temperature, so we want to identify the stress of a device from thermal impact. The most significant thermal impact comes from when the temperature is the hottest – typically in the manufacturer stage for an IC.
In typical advanced node processes, we conduct a rapid thermal anneal (RTA), which involves heating it to high temperatures for a short time. RTA should improve the crystallinity of the polysilicon and other design elements. But it does induce stress at that point due to the high temperature, and that stress remains. Think of it as little fissures or little cracks that you didn’t want to be there. Those weak points are going to get worse until they eventually fail. For chiplets, if you understand the manufacturing process and get information about the maximum RTA temperature, that’s a good starting point.
Material properties are another challenge for both thermal and stress. How much stress something can take depends on what it is — a piece of steel is stronger than a popsicle stick. For 3D IC design, understanding the material and manufacturing process is essential to understanding the historical stress.
The other part comes from when you’re in a heterogeneous environment – and the stresses come from what’s around you. Before silicon, you create transistors and some metallization and oxides on top that are well characterized. With the three-dimensional design, there are different processes and connections with metal through a package or TSVs or with Microbox. One of the biggest is ball grid arrays (BGAs) if you’re connecting that package onto a board somewhere, the BGAs are large and create a lot of stress. As you can see, we’re adding stress in ways that aren’t relevant in an SoC and design teams need to account for those new stress points and handle them appropriately. These impact system behavior or performance, and the system behavior or performance impacts the stresses and temperature depending on the frequency. High frequencies will be hotter than low frequencies. Using that information will help predict the thermal impacts in this system, thermal information, and physical information – ultimately determining the stresses. Both change the electrical behavior, resulting in potentially multiple cycles until closure.
When semiconductor design teams should start to ensure reliability in 3D IC design
To ensure reliability – you have to start early. But the earlier you start, the less you know. So, it’s an improve-as-you-go process. Determining the kind of heterogeneous 3D IC to build is a helpful starting point. If it’s unknown, you can start with individual dies as if they’re homogeneous structures and start putting them in place with their TSVs or other connections to assess potential thermal and stress problems. From there, you can place components on top of or next to others. You can play trade-offs at an early stage, but you’re missing some of the details.
For details, you need to know everything about the chipsets and the connections. As you start to add in more, you make decisions. Then continue through the cycle and make multiple rounds of analysis. Of course, you can find these things at the end as you put the design together. But as you move further along in the design, the more expensive it is to go back.
Designing a reliable package requires the design team to focus on analysis as early as possible, such as at the prototype and planning stage, and understand how it could drive mechanical stress and electrical-related failures. It’s more work than in the past, but that’s the benefit of it because you have so many more options. Semiconductor design teams have more room to be clever and find ways to do things not done before.
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View the episode transcript
[00:10] John McMillian: Welcome to the Siemens EDA podcast series on 3D IC design brought to you by the Siemens Thought Leadership Team. In our sixth podcast on 3D IC Verification and Analysis Workflows, we talked about what verification and analyses need to be performed on 3D IC heterogeneously integrated devices and why. Today, we will discuss the impact 3D IC has on device reliability, ranging from understanding thermal interactions within and between devices to the related thermo mechanical stress that can lead to warpage, cracking of micro bumps, hybrid bonds, and beyond. We will also look at electrical reliability from the aspects of latch-up, prevention, and ESD protection. Now, I’m pleased to introduce my special guest, John Ferguson, who is the Product Management Director of Calibre DRC Technologies at Siemens Digital EDA. Welcome, John, thank you for taking the time to talk with me today about 3D IC reliability. And before we dive into the discussion, would you mind giving our listeners a brief description of your current role and background?
[01:13] John Ferguson: Sure. Among other things, in addition to managing Calibre DRC, I also am over [01:20 inaudible] of the various products that we have from the Calibre side in the heterogeneous multi-die 3D IC space, and that’s kind of what brings me here today.
[01:35] John McMillian: There’s been a great deal of growth and development in the area of advanced heterogeneous packaging in the past several years. Aside from design analysis, what challenges do such heterogeneous assemblies need to overcome to ensure reliability?
[01:50] John Ferguson: That’s a great question. Reliability has been an issue even in the IC space for a couple of processing nodes now. It’s been around for a while, but it used to be you could handle it with DRC rules. Now, it’s gotten to be much more challenging. Now you see situations where a die can be DRC-clean or LVS-clean, but maybe it still fails on the manufacturing floor. Or worse, it works just fine on your test bench, but when you actually sell it out into the field and it’s in use, it fails unexpectedly and prematurely for your customers’ desire. It’s a scary situation for people who are in the IC space, particularly at the more advanced nodes, there are solutions in this space already for that — Calibre PERC is a really great example of that. The kinds of problems that we see in the IC space, we’re now also starting to see at a higher level from these heterogeneous 3D IC environments. It shouldn’t be all that surprising, these things really are formed by how your devices and your wires interact with each other. And that doesn’t really change whether you’re connecting things within a chip or across multiple chips or chiplets. The problems are still there, larger ESD are perfect examples. There are other cases as well; things like electrical overstress, different kinds of scenarios where you can have these failures. Especially, if you’re targeting applications that are going to be in automotive or in Mil-Aero kinds of applications, you really can’t have those things going down. You don’t want to be out on the road and all of a sudden your car drops dead in the middle of traffic. These things need to be carefully addressed and carefully monitored. I won’t spend too much time talking about what these things are because I think most listeners are probably already familiar. Basically, in a nutshell, latch-up is kind of a way where you can get two things inadvertently shorted together; they’re toggling together. Usually comes with a high voltage that’s enabling it, something larger than expected, but those things can and do happen.
[04:32] John Ferguson: Typically, we think of ESD as a human finger, walk around and scuff your feet especially as the weather gets colder, you pick up charge, then you touch a chip somewhere and that charges is dissipated into the chip, and it can blow up your transistors, and that’s obviously not a good thing. But it’s not just human discharge that can cause this. There are lots of places, both in the manufacturing side and in the use of your application, of your chip, and that can cause unexpected charge to suddenly appear on your input somewhere and cause catastrophic events. In SoC, it’s not too bad because we can find these situations. Even in the more complex scenarios, with tools like Calibre PERC, we can find them. And there are known solutions for how to address them. In the case of latch-up, you want to have a good guard ring, make sure that you have a sufficient amount of taps and current ties. On the ESD side, it’s really about making sure that you have sufficient protection pads. When you do have this unexpected charge all of a sudden appear, you can give it a fast path to ground as opposed to going through your transistors. That’s the good thing. The challenge in the 3D space is it’s not like what we do in an SoC where everything is in a single process, we know how to characterize it all upfront. You’re connecting things that come from multiple different sources that have slightly different behaviors, potentially, from one die to the next. And the remedies that you would apply, there is some process dependency on what you would have there. So, you have to make some decisions about if I have, for example, some ESD issue that is a combination of multiple dies, you need to think about “Which die do I place the fixes in? Or do I separate them across multiple dies?” It’s not necessarily complicated, but it’s something you need to think about. The size of your protection devices, for example, might change, depending on the process of your individual chiplet that you’re looking at. So you might have to make some decisions about “Can I fit sufficient protection devices in that region or not?” So, it’s interesting, but certainly, it’s all doable. It’s something that users are more or less used to doing in SoC design, so it’s not a big leap. What I think becomes challenging and where we’re going to discuss next is what are the scenarios where we don’t really have to spend a lot of time thinking about them today but we’re going to have to do much more. And those are the areas of thermal and stress, that we can come to in the next sections.
[07:46] John McMillian: Well, it’s very obvious that proper electrical design can avoid reliability issues. Do heterogeneous integrations introduce other reliability issues?
[07:57] John Ferguson: Yeah. Thermal is a perfect example. Of course, there are thermal concerns on a single process SoC, of course. But again, they’re largely addressed. If you are following your design rules appropriately, you’re not doing things that you weren’t expected to do with the design, then it’s generally going to behave. But we know, as you’re applying heat, that your transistor is dependent on the temperature that it’s operating in. As you heat things up the electrons and the holes that you’re trying to push through very, very tiny areas, those get heated and that heat gets dissipated out to the neighboring environment. So you can start to move that heat around a little bit; the more that you’re toggling a transistor, and the faster you’re toggling that transistor or the more current you’re trying to push to make that happen, the hotter it’s going to get. So, as you have transistors that are close to each other, then they start to heat up together. And again, in an SoC, you can handle that with design rules. I have design rules that are like, “I can’t have transistors too close together.” And that helps us to avoid this problem to a large extent. That part’s good, but when we get to multi-die chiplets and heterogeneous processes, things start to get a little bit different. And particularly, this starts to get to be interesting when we think about what we traditionally call floor planning. In an SoC, you do floor planning to say, “I’ve got this plane, where am I going to put the different components I want put on this chip in order to get all of the behaviors that I want to get in there optimal setting.” It’s weird to say floor planning for something that’s 3D because not everything’s on the same floor anymore if you will. But the concepts are still there. You don’t really want to have things that toggle very fast and are used frequently. Like a GPU and a CPU, generally, you wouldn’t want to put them close together on an SoC because both of them are getting hot. So you space those out a bit. Now, you’ve got to think about that from a 3D perspective as well. So, again, I wouldn’t want to put my GPU on top of my CPU or vice versa because now that he is not just dissipating in the horizon plane, but also up and down in space. So you can affect transistors that are below you or above you, that’s not always obvious to people. There’s also another concern associated with that, which is, particularly when you’re stacking die on a traditional SoC, all your transistors are right there on the silicon plane, and there’s a very clear path for how temperature is dissipated, how the heat is dissipated, it goes through that substrate. But if you’ve got multiple dies that are stacked up—and particularly if you’ve got thin dies, which is often the case—then you’ve got a hot temperature in one that maybe has no place to go.
[11:33] John Ferguson: And particularly if you’re talking about copper-bonded dies that are face-to-face bonded, then on the top tier, you may have a silicone component, but the heat is also going to come downward. That heat has no place else to go, but to the transistors that are on the die that’s bounded below it. And it’s a lot longer path before you get to an actual thermal escape, a thermal sink for you to take that heat away. What that basically means is that the temperatures are hot and they stay hot longer. So, that’s also a concern that needs to be considered. There are a lot of different issues in there. There are, again, mitigating factors for those things. You can put a TSV through your silicone, and that will help you to dissipate the heat faster. You can have “Through Insulator Via” or whatever you want to call it. But basically, something that acts like a chimney that will bring your heat all the way through so you can place those at the top die, going all the way down through the bottom die, and even through the silicone into the bottom die. But these things take up space, they have other issues with them, they will induce stresses that you don’t necessarily want. Stress also has issues that will cause your transistor to behave in unexpected ways. So, it’s all a very intricate mesh, if you will, even things like latch-up there, again, will become part of the problem because you’re adding in new potential ways. And your temperature is also going to have an impact on how those electrical behaviors present themselves, if you will. It’s the big challenge is you can’t really do these things in isolation. You have to really understand a whole system from a multi-physics perspective, to understand how it’s going to behave when you’re designing this thing. That’s what makes it very tricky. It’s not necessarily an easy thing to do, to know upfront what’s the best way to design a 3D IC. I sometimes say that the best thing about having the ability to do 3D IC design is that you have now many, many more options on how to do your design than you used to. You really opened it up in all new dimensions. But the worst thing is, you now have many, many more options. And identifying what are the best options for your particular needs, it’s a lot more work than it used to be.
[14:26] John McMillian: Well, it’s obvious that thermal can be a real issue in heterogeneous integrated packages, and it can’t be ignored or left to the end as an afterthought. But what about stress? You mentioned thermally induced mechanical stress. Can you explain what that is and how it’s related to thermal?
[14:47] John Ferguson: I’m not talking about the stress you get at work but the mechanical and physical stress. I think we all know what it is. You put a heavy piece of concrete on what you thought was going to be a straight board, the board bends right or maybe it breaks. We understand that, inherently, most people understand that stress and temperature are interrelated, but sometimes it’s easy to forget. I typically go back to the very, very basics, which is the old ideal gas law: PV=nRT. So, pressure, volume, and temperature are all interrelated. We’re not talking necessarily an ideal gas, it’s still basic concept hulls that as temperature goes up, then your stress is also going to go up; as temperatures come down, your stresses go down, and vice versa — assuming volume is held constant. So, this is another issue, as you put stresses on your transistor, we know that the transistor is going to behave differently. And again, this is not a new problem. We’ve known this for a long time. In the IC-SoC space, we started really having to address this around the 90 nanometers. So, it’s been there for a while. And again, the way we do it, traditionally, in an SoC is in the LVS space. LVS into the post-layout simulation space, where you say, “Okay, as I look at each transistor in context, with whatever else is in that surrounding, what stresses does it have?” We capture those as properties on the transistor, and then you can use that to feed into your transistor model for electrical analysis. Again, I’m a little bit oversimplifying it because we’re talking here, primarily, about stress. But temperature creates stress, and stress creates temperature, so you can’t really think about one without the other, I would say that in IC manufacturing stage. So, typically, what we really care about is, when it comes to stress of a device from thermal impacts, the biggest thermal impacts come from when the temperature is the hottest. And the temperature is the hottest for an IC in the manufacture stage. In typical advanced node processes, we do what’s called a rapid thermal anneal (RTA). You heat it to very, very high temperatures for a very short amount of time. And the idea is by doing that, you improve the crystallinity of your polysilicon and other elements of the design. But it does induce stress at that point because you now have quite a very high temperature that silicon, again, has been stressed. So that stress remains after the fact. Think of it as little fissures or little cracks that you didn’t want to be there. So, as you go forward and you begin to use this electrically, naturally, those are weak points; they’re going to get worse and worse with time until eventually, they fail. The good thing is, in most of those scenarios, really all you have to think about is what was that maximum temperature? So, if we’re talking about chiplets or chips more than one in a design, if you understand the process that was used to create it and if you can get information about what was that maximum RTA temperature, then you’ve got a good starting point.
[18:50] John Ferguson: Another challenge both for thermal and for stress is the material properties. How much stress something can take depends on what it is — apiece of steel is gonna be stronger than a popsicle stick. You need to understand what is that material. But again, it’s not just the material, it’s what it’s gone through in the manufacturing process. So, that’s a little bit tricky. Even predicting that is complicated. So, usually, it means that there’s a level of validations that you have to do, there are some measurements that should have to be done either by the foundry that makes each individual chip or chiplet or on the user’s end to make sure their results that are going to be predicted are accurate, but you can do it. The other part kind of related to what I was talking earlier about thermal, a lot of it comes from when you’re in a heterogeneous environment, the stresses come from what’s around you. Before you have a piece of silicon, you create your transistors, there’s some metallization and oxides on top, but you can pretty well characterize those. Now, when you go to something that’s three-dimensional, and there are different processes, and you’re connecting them up with metal through a package or through TSVs or you’re connecting with Microbox. And really even the biggest one is the BGAs if you’re connecting that package, once it’s done, onto a board somewhere, and those BGAs are quite big, so they’re creating a lot of stress. So, you’re getting this introduction of things that are adding stress that you didn’t really have in an SoC. So, you’ve got to make sure that those are being taken into account and handled properly. That’s basically how it goes in. And again, it’s not a simple thing; you can’t just say, “Well, I did a thermal analysis and so I’m good,” or “I did a stress analysis, then I’m good.” Both of these are going to have an impact on your system behavior or performance. But also, the system behavior or performance has an impact on the stresses and the temperature because if you’re driving a device at high frequencies, it’s going to be hotter than if you’re driving it at a low frequency. So, you get this kind of circle, you say, “Okay, I think I’m going to run it at this frequency. I’m going to use that information to help me predict what my thermal impacts in this system are going to be, thermal information, and the physical information. I’m going to figure out what the stresses are.” But then both of those are changing what your electrical behavior is. So, you have to go through potentially multiple cycles before you get closure on these things.
[22:07] John McMillian: That’s very interesting. So, given the comprehensive nature of ensuring reliability, where should the design teams start?
[22:17] John Ferguson: This is hard. This is the challenge. You’ve really got to start early. But the earlier you start, the less you know. So, it’s kind of an improve-as-you-go process. But you can do things early on. If you know the kind of heterogeneous 3D IC that you’re going to build, then that helps you a little bit. And even if you don’t know, you can start with very simple, let’s treat the individual dies as if they’re homogeneous structures, start putting them in place with their TSVs or whatever you’re going to do to connect between them, you can start to get some idea there about where do I have potential thermal problems? Where do I have potential stress problems? So, you can make decisions about what do I place on top of what or next to or can even maybe make decisions about “Do I want to have die-to-die with bumps? Or do I want to do face-to-face bonding?” Whatever it might be, you can kind of play trade-offs at an early stage. The issue is that you’re missing some of the details. If you want to get the most detail, you need to know about everything in all the chipsets and what’s outside that’s connecting them together and connecting them to the rest of the world. As you start to add in more, as you make initial decisions and you start to add more, you have to continue to do your analyses on these. And again, it’s not just one analysis, you’ve got to cycle through and do multiple analyses on that to figure out where all of this goes. That’s probably, I think, what I would like to mainly get to the user is be prepared to have thought this through early. Of course, you can find these things at the end, as you put the design together. But once you’ve gotten that far and now it’s a very expensive proposition to go back and start all over again. If you find you have a severe problem, my recommendation is to start early and keep monitoring as you continue your design through the process.
[24:48] John McMillian: So, designing a reliable package really does require the design team to focus on analysis as early as possible, such as at the prototype and planning stage, and understand how it could drive mechanical stress and electrical-related failures. Thanks a lot for that information. Before we end this podcast, are there any final words you’d like to leave the listeners with?
[25:09] John Ferguson: I would say, keep what I said in mind that start thinking about this early, think about it throughout your design process as you’re iterating through and making those decisions. Know these things are tricky. There are things you can do, just like you can in an SoC, where you can find known good die. There are ways to do tests on the whole package to make sure things are good. But even then, it may be good when you’re doing that test analysis, but is it going to be good in the field? That’s really why you care about these things. It’s important to keep them in mind. And I think this is probably the area in the 3D IC space, where you really do have an extra burden of work than you do in the SoC space. It’s more than you had to in the past. It’s not that it’s a new or different phenomenon, but it’s harder to calculate the phenomenon, and it’s harder to put in place guardrails that will prevent you from making mistakes early because of the fact that we’re giving so many more options. And again, that’s the benefit of it; because you have so many more options, you’ve got a lot of room to be a clever engineer and find ways to do things that nobody’s ever done before. You just have to be prepared to make the trade-offs of keep validating that there’s not something unexpected going to happen with your clever idea before you go down that path.
[26:49] John McMillian: Thank you, John. Thanks for this highly informative discussion on this seventh podcast on 3D IC, and we look forward to future podcasts with you on the same topic. Also, we want to thank you, our listeners. And if you’ve not done so already, be sure to subscribe so you don’t miss the next episode of this podcast series on 3D IC.
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