A “big rock” approach to DC drop analysis in IC package design
The key analysis needs of high-performance computing semiconductor package design
Today, power requirements are continually increasing as you bring more die/chiplets into a package, which becomes a big challenge from a power delivery perspective. Being able to analyze the core power and understand if you have enough vias and copper for the IC current requirements is essential to success.
Having more and more die/chiplets in a design makes the power delivery more challenging. When you have a single monolithic die, the power delivery problem is fairly straightforward (yet can still be tough depending on how many power domains you have). You know the voltage coming in, and you know the peak current demand on the rail your device requires. You might have some things that you want to do from a core power analysis perspective to validate that you have good connectivity, but it’s not as challenging as once you start throwing multiple die into a system like with high-density heterogeneous packages.
In that case, not only do you have the issue of trying to deliver power through multiple rails, the current delivery path complexity increases since you now have multiple die in different locations pulling current from the rail. Additionally, you’ve got less room than you would have in a single monolithic package to be able to supply voltage and current to the die. With these increased densities, you may not have enough copper to meet the design requirements of all the chiplets which can result in additional layers in the package just to support the current requirements for all these different die.
To ensure that you’ve got the right architecture and ability to deliver power to all the chiplets in these complex HDAP (high density advanced packaging) designs, you really have to have tools like HyperLynx DC Drop to be able to predict the design behavior early and make the right layout trade-offs.
The capacity challenge
Across the HDAP industry, designers are challenged by the capacity of their tools from a design an analysis perspective. There are so many vias and so many pins that DC drop analysis or any other type of analysis is a challenge. It’s stretching EDA tools to their limits.
The standard methodology would be for a package designer to get everything routed and then hand off to a PI expert for sign-off. They may then suggest changes to the power delivery to optimize for the design requirements, but by the time that feedback comes back to you, the packaging designer, it basically means a complete rework of the design, making the cost of change significantly higher compared to if they had gotten that input much earlier in the design process.
In the Xpedition package design flow, we are making a methodology change recommendation. You really need insight into performance earlier in the design process and put capability into the hands of the package designer. Having good analysis capabilities integrated with your packaging design flow enables you to do an analysis of power rails right in the tool you’re familiar with.
The idea here is that we’re enabling designers to get good enough information to make design choices and improve design quality before it gets to a final sign off state. What do I mean by “good enough?”
The “big rock” approach
Try to identify big problems (rocks) early on to improve your end results. We’re not trying to dig down in the weeds and seek the highest level of accuracy for sign-off purposes. You’ve got a boulder in the road, and you can’t move forward because you know there’s a boulder there. If your eyes are open, you can see the boulder. But if they’re not, then you just don’t know. So, the big rock approach is basically opening somebody’s eyes to the possibility of a problem that they wouldn’t have seen otherwise, as soon as you can, to avoid costly changes and delays.
An example customer’s design flow
One of our customers has implemented this big rock approach using Xpedition Package Designer (xPD). Inside of xPD there is a form to enter some very basic information about the die or the components that are in the design. For example, on a particular die and power rail, lets say we make an assumption of even current distribution and have ever bump consume 15 milliAmps. Maybe some bumps draw more, some less, but we’re not trying to be perfect here, we just want to find the boulders.
Once the package designer has the that basic information, we make it super simple for them to fill in a current value for the voltage rail and do it all from within the Xpedition Package Designer tool. They can run the analysis automatically from within the environment they know, which is xPD, and it produces results in HyperLynx. Those results then feedback in to xPD so the user can see that they’ve got a violation at this location where their current density is too high, or a via is overcurrent, or they’ve got too much voltage drop. Those violations feed back into xPD on the layout, so the designer can click on it, zoom to that area automatically where the problem is, fix it, and then rerun the analysis.
DC drop analysis with Xpedition Package Designer and HyperLynx
With our solutions, we enable our customers to do analysis of power rails right in their own package design environment. They can do this while the planes are being routed so they can modify the design and quickly see if the changes they made are improving the performance or not and make a decision to move forward. This gives designers a lot of flexibility and in the end, results in a high quality design for the PI engineer to do final sign-off on.
To learn more about xPD download this eBook: the six differentiators of xPD, or request a demo today.
