The role of AI-infused EDA solutions for semiconductor-enabled products and systems

Discover why semiconductor-enabled products and systems are demanding AI-infused solutions and how AI is changing the nature of semiconductor design.

Discover how AI is changing the nature of semiconductor design

AI is shaping the semiconductor industry’s future and its alignment with Siemens’ commitment to innovation and enhancing sustainability by accelerating…

Assembly Verification Flow for Silicon Interposers with Embedded Deep Trench Capacitance

User2User 2024: Assembly verification flow for silicon interposers

In this User2User 2024 session Broadcom’s Suvarna Vikhankar presents “Assembly Verification Flow for Silicon Interposers with Embedded Deep Trench Capacitance”

Parasitic extraction technologies: Advanced node and 3D-IC design

Advanced nodes and 3D-IC packages require new and enhanced parasitic extraction processes that can resolve a variety of complex parasitic issues in these designs.

System-level, post-layout electrical analysis for high-density advanced packaging (HDAP)

HDAP designs like FOWLP need post-layout simulation (analog) and post-layout STA (digital) flows to augment basic physical verification DRC and LVS.

Understanding 3D IC Technology: Unveiling the Future of Integrated Circuits

Delve into the world of 3D IC technology, its architecture, benefits, and applications. Learn how it’s reshaping the future of integrated circuits for enhanced performance and efficiency.

SemiWiki Podcast – An expert panel discussion on the move to chiplets

Listen in as Tony Mastroianni Advanced Packaging Solutions Director – Siemens EDA along with Saif Alam Vice President of Engineering…

An image of a PCB with text that says IC Packaging 2.13

What’s new in Xpedition IC Packaging release VX.2.13

The Xpedition high density advanced packaging solution it is made up of two core products, Xpedition Substrate Integrator (xSI) which…

Illustration that says next generation IC Packaging part 4

The five keys to next-generation IC packaging design: Part 4

“Golden signoff” – The final step in the semiconductor packaging process In my last blog post, I talked about the…