HDAP designs like FOWLP need post-layout simulation (analog) and post-layout STA (digital) flows to augment basic physical verification DRC and LVS.
3D IC package designers need assembly-level LVS for HDAP verification.
Part 1: An advanced IC packaging design and verification solution For many applications, next generation IC packaging is the best…
Over last 2-3 years, everyone has been talking about Moore’s “Law” becoming invalid. Even if it does, we will continue…
If you’re involved in semiconductor package design using routable substrates — that is, as opposed to leadframe based — then…
Semiconductor package design industry in 2023 expects to see accelerated growth of heterogeneous integration resulting emergence and adoption of new technology.
