Semiconductor Packaging

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Monolithic scaling limitations drive the growth of 2.5/3D multi-chiplet, heterogeneous integration that enables PPA targets to be met. Our integrated flow addresses prototyping challenges to signoff for FOWLP, 2.5/3D IC, and other emerging integration technologies.

Learn more about semiconductor packaging design and verification.

Featured posts

Image showing physical design IP reuse with Xpedition Package designer

Embracing physical design IP reuse as a best practice

July 22, 2024

Efficiency in IC package design is becoming more important as design cycles shorten and complexity surges. One common approach to…

By Keith Felton
2 MIN READ
New innovative way to functionally verify heterogeneous 2D/3D package connectivity

New innovative way to functionally verify heterogeneous 2D/3D package connectivity

June 6, 2024

This blog introduces a white paper that addresses the challenges of verifying
package connectivity and illustrated how to use formal tools to verify connectivity for package designs.

By John McMillan and Todd Burkholder
3 MIN READ
Two people working at a white board with text onscreen that says: Multiplying engineering resources for efficient package substrate design

Multiplying engineering resources for efficient package substrate design

May 14, 2024

In the world of package substrate design, the age-old saying, “many hands make light work,” holds more truth than ever….

By Keith Felton
2 MIN READ

Latest posts

Engineer seated at computer studying physical prototype for early planning of interconnect systems and design verification workflows

Importance of early planning for interconnect verification in 3D IC physical design workflows

October 24, 2022

In our last podcast on 3D IC architecture workflows, we discussed how a system or microarchitectures determine how to partition…

By Heather George
16 MIN READ

The five keys to next-generation IC packaging design: Part 2

October 19, 2022

Multi-domain integration enables faster time to market for complex advanced semiconductor packages with a seamless integration of design and verification.

By Keith Felton
2 MIN READ
3D IC design engineer using gloved hands to inspect and verify components

Front-end architectural verification considerations for 3D IC design

October 11, 2022

So far in our 3D IC blog series, we’ve discussed efforts to create chiplet ecosystems, design workflow changes needed to…

By Heather George
18 MIN READ
what's new in Xpedition IC Packaging

What’s new in Xpedition Advanced IC Packaging release VX.2.12

September 19, 2022

The Xpedition high density advanced packaging solution it is made up of two core products, Xpedition Substrate Integrator (xSI) which…

By Keith Felton
3 MIN READ

The Five Keys to Next-Generation IC Packaging Design: Part 1

September 7, 2022

Part 1: An advanced IC packaging design and verification solution For many applications, next generation IC packaging is the best…

By Keith Felton
2 MIN READ

3D IC verification requires a golden netlist that allows exceptions

August 29, 2022

With current 3D IC packaging technologies, since the system-level netlist (the 3D IC design intent) drives system-level LVS verification, designers…

By Tarek Ramadan
< 1 MIN READ

Megatrends of advanced IC packaging solutions 

August 25, 2022

Over last 2-3 years, everyone has been talking about Moore’s “Law” becoming invalid. Even if it does, we will continue…

By Keith Felton
3 MIN READ
IESF 2022

Learn about heterogeneous integration of semiconductors for autonomous driving, electric vehicle, and ADAS systems at the IESF 2022 automotive conference

August 18, 2022

IESF Automotive began 22 years ago and has been a must-attend event for automotive E/E design experts and executives throughout…

By Keith Felton
2 MIN READ
Evolution of 3D IC Architecture and the impact to design flows

Evolution of 3D IC Architecture and the impact to design flows

August 11, 2022

In our last blog about 3D IC, we discussed the models chiplet vendors need to provide System-in-Package (SiP) integrators to…

By Heather George
10 MIN READ