By Rahul Singhal, Mentor Graphics

Near-zero defect testing for safety-critical ICs means also testing the DFT logic.

Integrated circuits (IC) are a big part of our everyday lives. ICs are used in almost all the systems whether they are for entertainment, productivity, healthcare, automotive or other applications. When it comes to IC-testing, the requirements are determined by the application. An IC used in a safety-critical application such as an airbag deployment system requires higher testing standards than the one used in a digital watch.  A Design-For-Test (DFT) solution for safety-critical automotive ICs must ensure that there are no manufacturing defects by providing high test coverage. The Mentor Graphics’ automotive DFT solution called Hybrid TK/LBIST enables users to get test coverage of ~100% while also controlling test time and cost.

Mentor Graphics solution for high test coverage in automotive applications

ICs used in safety-critical automotive applications must have near zero-DPPM (defective parts per million) and high test coverage approaching ~100%. An IC design includes both functional and DFT logic and even with 100% test coverage of the functional logic, defects can still be present in the DFT logic.  To ensure a defect-free part, the DFT logic must be tested in addition to the core logic. Mentor’s Hybrid TK/LBIST automotive test solution combines two DFT components—Tessent TestKompress (TK) for manufacturing testing and Tessent LBIST for in-system testing. To ensure the high test coverage of the entire chip, the solution also provides a mode called Controller Chain Mode (CCM) to specifically test the hybrid DFT logic. The total test coverage of hybrid logic, as determined by using CCM in combination with existing core test patterns, is 99%.

Mentor’s automotive test solution also includes the Tessent MBIST solution for testing embedded memories in automotive ICs. Tessent MBIST, which includes an MBIST controller and a memory interface, allows for the MBIST controllers to be tested with scan insertion and is also capable of at-speed scan testing of the memory interfaces. Our automotive test solution is based on IJTAG infrastructure, which is also tested in CCM.

Controller Chain Mode (CCM) for Hybrid TK/LBIST logic testing

CCM can be optionally implemented during insertion of the Hybrid TK/LBIST logic. When enabled, CCM provides controllability of the Hybrid TK/LBIST flops and registers and of IJTAG segment insertion bits (SIBs) by connecting them serially in a chain. The ATPG tool then generates patterns for CCM by targeting faults in the DFT logic.  The CCM chain can be viewed as a scan chain for the hybrid logic and IJTAG SIBs with its own ccm_scan_in, ccm_scan_out and ccm_en ports. It is a separate chain from the scan chains in the core and is not controlled by the scan compression engine (TK). The ccm_scan_in and ccm_scan_out are used to shift the CCM scan pattern in and out respectively. The ccm_en port enables the CCM by selecting the CCM chain path in the DFT logic. These port can either be dedicated ports at the top level of the chip or shared with existing ports. The test coverage of Tessent Hybrid TK/LBIST determined by CCM mode alone is 96.8%. The following diagram shows the implementation of CCM.

Figure 1: CCM path through Hybrid TK/LBIST and IJTAG SIBs. An IJTAG SIB is programmable bypass register that controls the inclusion of a scan-path segment into existing scan path.

Hybrid TK/LBIST test coverage

Through experiments, we determined the test coverage of Tessent Hybrid TK/LBIST to be 96.8% using CCM. However, the test coverage should be close 100% in order to meet automotive IC testing requirements. We targeted the remaining faults in the Tessent Hybrid TK/LBIST test logic by fault simulation using a small subset of existing core test patterns. That brings the cumulative test coverage of Tessent Hybrid TK/LBIST to 99%.

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