The growing presence of IC Test and Yield Analysis at DAC

By Tessent Solutions

DAC was once the playground for the core EDA topics but has broadened in a reflection of the growing connectedness of all aspects of getting an electronics product from concept to release into the world. In addition, you now see a focus on market segments because the needs for, say, an IoT application are much different than those for an automotive application.

IC test has become a more visible player in the EDA space, and is not considered just a product engineering issue. From early in the design stage until well after product deployment when defective parts are returned for analysis, test is part of the story. Test is Design-for-test, manufacturing test, and failure analysis are critical to managing the cost and time-to-market of today’s large SoCs. New test technologies are vital for meeting the ISO 26262 safety and reliability standards for automotive ICs.

In reflection of the fact that DFT is no longer an EDA afterthought, but a key ingredient of making electronics for the fastest-growing markets, the number of quality of test-related sessions at DAC is growing every year. Mentor’s DFT and yield analysis group is leading the trend.

Here are three sessions you can register to see at the Mentor booth:

Bench top debug of ATPG patterns with Tessent® SiliconInsight®
- Reducing the silicon bring-up phase is critical in getting new ICs into the hands of customers. Turning chip level test failures into actionable results requires detailed knowledge about the DFT architecture as well as how test patterns are turned into a test program. In this presentation, we will demonstrate new technology for bench-top debug and characterization of ATPG patterns without the need for costly ATE time. Within the same Tessent platform that generates patterns and diagnoses failures, you can now apply tests and capture results. Learn how you can reduce the silicon bring-up cycle time with Tessent SiliconInsight for ATPG and an off-the-shelf hardware adaptor.
Get DFT out of the critical design path with true hierarchical DFT
- In a traditional design flow, much of the DFT work that changes the design occurs late in the design cycle and manufacturing test pattern generation is in the critical path of design completion. With Tessent TestKompress, this no longer has to be the case. Using a hierarchical DFT methodology, pattern generation is performed concurrently on the blocks early in the design phase as soon as each block is ready. The patterns are then automatically reused, mapped, and merged at the top-level design. Pattern generation for blocks is taken out of the critical path and is often 10 times faster with a smaller workstation. Manufacturing test cost is significantly reduced using channel sharing. Learn how you can adopt the industry’s most comprehensive hierarchical DFT solution, and discover how you can take advantage of many of these benefits today without modifying your design.
Test Solutions for the Automotive Market
- The amount of electronic content in passenger cars continues to grow rapidly, driven mainly by the integration of various advanced safety features. The industry’s move towards fully autonomous vehicles promises to even further increase the number of these safety features and thus electronic content. It is of course critical that these safety-related devices adhere to the highest possible quality and reliability requirements. These requirements are formalized in the ISO 26262 standard that is being rapidly adopted by automotive manufacturers and suppliers worldwide. The Mentor Tessent product family offers a comprehensive set of test solutions to address the quality and reliability metrics mandated by the ISO 26262 standard. Central to these solutions is the new Tessent MissionMode architecture which provides system-level low latency access to all on-chip test resources for on-line test and diagnosis.