RTL hierarchical DFT and ATPG reference flow for Arm cores

By Tessent Solutions

Mentor and Arm® teamed up to create a new reference flow for performing register transfer level (RTL) hierarchical DFT and ATPG on Arm cores. If you are designing with IP subsystems from Arm, this flow is for you.

Mentor and Arm have maintained a long-term partnership to improve testing of Arm cores. Arm and Mentor know that our customers are integrating hundreds of IP subsystems on their SoCs, including processors like the Arm Cortex®-A75 (Figure 1), and would benefit from a reference flow. Success for designers is easier when their EDA and IP vendors cooperate, which is why Mentor and Arm have continued their closer partnership in developing reference flows for so many years.

Figure 1: Quad-Cortex-A75 subsystem design architecture.

This latest reference flow reflects the fact that large, complex, multi-core SoCs need better and more efficient strategies for DFT and ATPG. The adoption of hierarchical DFT has been growing quickly, as it proves its value for large, complex designs. With hierarchical DFT, all the DFT is completed at the block level and then replicated to the top level. Hierarchical DFT moves the DFT efforts early in the design flow and reduces ATPG runtime and compute resources by 10x.

This DFT flow provides a simple and verified hierarchical test methodology for cost-effective, high-quality test of Arm IP, making it easier to reap the benefits of hierarchical DFT. The flow defines all the steps necessary to implement RTL hierarchical DFT, including scripts, interfaces, and documentation.

The detailed flow is based on a test case as a bottom-up flow that starts with core-level RTL design (Figure 2). It takes you through every step with images showing the results of each step from core-level DFT to chip-level DFT.