How-to create comprehensive test coverage reports during hierarchical DFT

Rick Fisette – Mentor, A Siemens Business

This three-part video series shows how to use the Tessent Shell automation features to create a comprehensive test coverage report when using hierarchical DFT. 

Complex SoC designs typically consist of many physical design cores integrated together. When using Hierarchical Design-For-Test (DFT) techniques, all the DFT steps are completed at the core level first before moving to the top level of the design. This means there is test coverage information generated across many separate steps for each core which all has to be efficiently merged together into a single, comprehensive, and meaningful test coverage report.

Part 1 of this video series, “Full Coverage Accounting for SoCs,” provides an overview of the Tessent features that automate this process. Parts 2 and 3 demonstrate how to actually get it done in the Tessent tools when working at the core level and at the chip/SoC level.

In the 7-minute long first video of the series, we summarize the challenges of reporting test coverage, particularly in large hierarchical DFT designs. We then introduce the key technology that allows for better test coverage reporting: Tessent Shell. The Tessent Shell database unifies all Tessent products and fault classes, and finds and merges coverage information from different cores and test modes.

Next we introduce the automatic fault classification of DFT instruments. Part 2 of the video series (8 min long) demonstrates how test coverage information from DFT instrument (e.g. MBIST, OCC) insertion steps at the core level of a design is automatically forwarded to the ATPG step by Tessent for more accurate results. Detailed descriptions of fault categories in the statistics report are provided and results are also viewed in the DFT Visualizer graphical interface.

Part 1 describes how Tessent merges coverage for multiple cores and modes, and in Part 3 of this video series (10 min long), we demonstrate how test coverage at the core level of a design is automatically forwarded to the SoC level when using pattern retargeting. We also describe the process for generating External mode patterns and test coverage results, as well as merging Internal mode results from the core. Detailed descriptions of fault categories in the statistics report are provided and results are also viewed in the DFT Visualizer graphical interface.

The Tessent Shell database simplifies and automates test coverage reporting while generating more accurate reports, lowering ATPG runtime, and providing detailed fault categories for debug purposes.

Tune in to the three short how-to videos here:

Tessent Fault Coverage Accounting for Complex SoCs: Part 1 of 3

Tessent Fault Coverage Accounting for Complex SoCs: Part 2 of 3

Tessent Fault Coverage Accounting for Complex SoCs: Part 3 of 3