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Broadcom case study using Tessent Connect to build DFT flow for AI chips

Broadcom developed an advanced, highly automated DFT flow for some of it’s biggest chips targeting the artificial intelligence (AI) market using Tessent Connect, Mentor’s solution for optimal automation across Tessent products. This video, filmed during ITC in November 2019, features Chinmay Gupte, Director of Worldwide DFT for Broadcom ASIC Products Division, describing how Broadcom did it.

Increasing workloads are driving demand for new chips with higher performance per watt. The silicon also needs to have a quick ramp to production to get to customers faster. With a design phase of 9-12 months, they needed new ways to meet the aggressive schedules.

Broadcom had been performing test insertion flat, at the top level of the chip, which took several weeks. ATPG was a separate flow, which took several weeks. Yet another flow was run for the IJTAG implementation. One major drawback was that ATPG coverage and vector count wasn’t available until quite late in the design phase, which adds risk to the design schedule.

Gupte says the Broadcom ASIC division adopted a hierarchical DFT methodology a few years ago for their large, complex, custom designs at 16 nm and 7 nm with the goal of reducing time-to-market. With hierarchical DFT, they can finish test insertion and ATPG at the block level. In parallel, they do top-level test insertion on just the glue logic and blocks are represented as gray boxes.

They saw a 50% reduction in implementation time with hierarchical DFT. ATPG runs for stuck-at faults went from 4+ weeks to days, and they used smaller machines.

However, they still had room for improvement in their DFT process. Retrofitting an existing flat flow with hierarchical DFT steps requires a lot of manual intervention, which introduces errors and inefficiencies.

Gupte says his group adopted Tessent Connect to build a reliable, sustainable, and future-proof hierarchical DFT flow. Tessent Connect is not a product, but a method for advanced, end-to-end automation across Tessent tools that better connects the people, processes, and tools involved in the DFT work.

To hear details about Broadcom’s success with optimizing their hierarchical DFT flow, watch Gupte’s 12-minute presentation.

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This article first appeared on the Siemens Digital Industries Software blog at https://blogs.stage.sw.siemens.com/tessent/2020/02/28/broadcom-case-study-using-tessent-connect-to-build-dft-flow-for-ai-chips/