DFT and the competitive edge
Advanced DFT is your competitive edge
Every new SoC project starts with grand hopes of glory. This one will be on time and under budget. Those early hopes are usually curbed by the harsh reality of everything that can go wrong when designing a large, complex chip.
To stay competitive, the most successful companies continually refine and optimize all aspects of chip design and fabrication, including the increasingly important design-for-test (DFT). DFT encompasses a broad range of test-related design tasks, from insertion and verification of test logic during RTL design and continuing all the way to failure analysis of field returns and in-life monitoring of performance, faults, and security. Simply adding scan compression and creating traditional test patterns is no longer a recipe for success.
Today’s advanced DFT strategies ensure that a device meets quality and reliability requirements, and helps to improve yield, reduce costs, and get the product to market faster. Design managers should understand the elements of an advanced, smart DFT strategy and know how to go about building the best DFT for their needs.
To that end, we published a whitepaper that outlines the significant areas of research and development focused on solving DFT and yield challenges for today’s designs, including extremely large artificial intelligence (AI) processors that require hierarchical plug-and-play methodologies, and automotive applications that need very high manufacturing test quality and in-system test capabilities.
No matter what the specific DFT needs are for your design, there are some basic requirements for a DFT solution, including:
- It uses the most effective techniques for detecting manufacturing defects
- It integrates efficiently into various common design flows and functional system requirements
- It can leverage DFT and production test results to improve yield, which directly impacts both time-to-volume and profitability
First, find the defects
DFT must catch defects in manufactured silicon and ensure that a part is defect-free before it’s placed in-system. For some chips, specifically any IC in a safety-critical role, getting to near-zero defects will likely require the use of cell-aware fault models that can target potential defects within the technology cells. Major semiconductor companies, including AMD (Hapke, 2014) have seen dramatic improvements in fault coverage with cell-aware test. ATPG advances include new types of bridge, opens, cell-aware/timing-aware, and cell-neighborhood tests. These so-called “automotive-grade” test has been vetted by the likes of Intel and ON Semiconductor in published research papers (Howell, 2018 & Maxwell, 2017).
Using more test patterns to increase fault coverage can overwhelm available compute resources and tester capacity, but a new kind of test point was introduced that dramatically reduces pattern sizes. Companies like Broadcom (Konuk, 2015) have used these new test points to control the growth of test pattern counts. An even newer technology for logic built-in-self-test (BIST), called LBIST Observation Scan Technology, was designed specifically to improve in-system test speed for automotive devices.
Implementing hierarchical DFT for large designs is facilitated by newer, intent-driven automation that can work with higher-level user input.
Improve the yield
DFT can improve the manufacturing process and increase yield, which has a direct impact on business. Data from failed manufacturing tests can reveal valuable information about the mechanisms that cause the circuit to fail. Analyzing this data using scan diagnosis significantly speeds to time to find root causes of failure. Advanced scan diagnosis has been used by foundries like GLOBALFOUNDRIES to find root causes of failures more efficiently (Benware, 2012).
The aggregate data from a whole population of failing die across wafers and lots helps fix systematic yield problems that eat into profit. This volume scan diagnosis, an advanced technique that uses statistics and machine learning, is in use in many successful companies.
Streamline the DFT flow
A random basket of DFT tools won’t necessarily lead to the time and cost savings that chip companies need to be competitive. Your set of DFT tools work best when built on a shared database. A unified DFT platform can operate as an “intent-driven” environment, reducing the complexity of the DFT flow and accelerating time-to-market. Both eSilicon (Mentor press release, 2019) and Broadcom (ITC, 2019) described results including 50% reductions in implementation time with hierarchical DFT and a unified DFT platform.
Reliable DFT technologies aren’t developed by the EDA supplier in a vacuum, they require constant work with industry partners in order to mature into dependable solutions. For example, say you need to use cell-aware test but don’t want to generate the cell model library yourself. No problem; Arm® provides cell-aware library models for both ATPG and diagnosis. We also have complete reference design flows for with Arm and Samsung. ATE suppliers Teradyne and Advantest support over-the-cloud tester access and are partnering in 1149.10 high-speed IO scan test with Mentor.
In today’s competitive semiconductor environment, every part of the design flow, including DFT needs to contribute to your success, not create more barriers. Tessent DFT technologies, developed in partnership with leaders in the semiconductor ecosystem, are a low risk, trustworthy solution with a proven track record of success for the most challenging designs.
