On-demand Webinar: Faster DFT, better results
Webinar: Automation and plug-and-play DFT methods for fast time-to-market
Watch the webinar now: 1 hour
How would your design schedule change if you could dramatically reduce design-for-test planning and implementation effort?
Modern SoC (system-on-chip) designs present huge challenges in design size and integration, making them difficult to test using traditional scan access methods. Traditionally, designers can allocate compression channels from top-level pins to a core. They then have to iteratively optimize those top-level pins when cores change, which requires you to know the number of patterns per core. Pattern count isn’t usually known until well into the design cycle, putting compression challenges in the way of design schedule priorities.
SSN is the first DFT technology that doesn’t require global DFT signals (e.g., scan_enable and shift clock). The scan signals, generated local to each core by the ScanHost, can drive any number of compression channels and chains at the core level, decoupling the compression channels at the core from top-level pins.
Register for this webinar if you need to get a design to market quickly without spending a lot of time on DFT. The speakers will cover the advantages of using Tessent SSN to simplify timing closure and reduce time to market.
Who should attend:
- DFT design engineers/managers
- IC design engineers/managers
- Production operations teams
- Automotive IC design engineers/managers
What you will learn:
- How to manage modern challenges with SoC designs and DFT
- New approaches to SoC test
- How SSN enables a plug-and-play hierarchical DFT architecture
- How to enable SoC-level DFT solutions using SSN
Meet the trainers:
Ron Press, Director of Technology Enablement, Siemens EDA
As a 30-year veteran of the test and DFT industry, Ron has presented seminars on DFT and test throughout the world. He is a member of the International Test Conference (ITC) Steering Committee. a Golden Core member of the IEEE Computer Society and a Senior Member of IEEE. Ron has patents on reduced-pin-count testing, glitch-free clock switching and on 3D DFT. Ron started his work in the test industry at Raytheon Company working on test and consulting throughout the company on test and built-in test.
He co-developed the Testability Design Rating System (TDRS) for the US Air Force and received the Raytheon inventor’s award for a built-in test analysis system. Ron led the development of a state-of-the-art RF/digital tester at Harris RF starting in 1995. He has been with Siemens since 1997.
Peter Orlando, Product Manager, Siemens EDA
Peter is the SSN Product manager and part of the Siemens Tessent DFT Product Marketing team. Since joining Siemens 2018, Peter has been part of the development of SSN product and primarily responsible of the successful deployment of SSN. As the customer-facing technical lead for the SSN product, Pete has been providing implementation guidance to external customers and internal colleagues. He’s been part of many designs that have successfully taped out with SSN. Pete’s role in SSN continues to expand with the development and deployment of new features being added to regularly. Prior to joining Siemens, Peter worked in the silicon industry for 25 years, mostly in the field of DFT, for such companies as Marvell Semiconductor, Micron Technology, ST Microelectronics, and LSI logic.
