Yasa! Mentor Focus at the European Test Symposium

The IEEE European Test Symposium  takes place from 22-16 May in Limassol, Cyprus. When not contemplating the stunning azure Mediterranean, be sure to catch up on what’s new with Mentor’s Tessent IC test and yield analysis solutions. Mentor’s Tessent product line covers everything from test definition, test bring-up, silicon characterization, water test, package test, failure diagnosis and yield analysis for IC logic, memory, analog, and I/O.

At the Table-top Demo session, you can see how to use a simple benchtop system for silicon debug, characterization, and diagnosis. The benchtop debug system reduces overall test cost and time-to-market.

Mentor will also give two presentations at the Vendor Sessions. The first is “Full Throttle on Automotive Test,” which describes Mentor’s comprehensive set of targeted test solutions to meet ISO 26262 quality and reliability requirements. All Tessent solutions are part of the Mentor Safe program and are ISO 26262 certified for use on ASIL D designs.

The second Vendor Session presentation is “DFT Methodologies and IoT Trends,” which clarifies the unique manufacturing test challenges of different market segments and how DFT methodologies will change for the fast-growing IoT sector.

Panels

If AMS is your area of concern, you might want to go to the technical session titled “A Publically-Accessible set of AMS Benchmark Circuits,” by Stephen Sunter. Sunter is also moderating a panel session to discuss the most significant defects that we are not modeling or targeting adequately.

If automotive ICs are more your thing, visit the concurrent panel on in-field self-test for automotive ICs. Mentor’s Martin Keim and others will discuss the issues surrounding this growing market.

The final panel of the symposium, “Industry Wish List,” includes foundry, EDA, and semiconductor perspectives on the needs and wants of IC test.

Technical Sessions and Tutorials

• “Bridge Over Troubled Waters: Critical Area Based Pattern Generation,” presenting research conducted by ON Semiconductor and Mentor.
• “ROM Fault Diagnosis for O(n^2) Test Algorithms,” presenting research conducted by Poznan University of Technology and Mentor.
• “Volume Diagnosis Data Mining,” is a tutorial session that will be useful for the failure diagnosis crowd.

TESTA 17 Workshop

Finally, consider attending the TESTA 17 workshop. It starts on Thursday 25 May with wine and cheese and some casual presentations. The technical sessions begin on Friday 26 May. You can download the program (PDF). The first morning session is a tutorial on emerging standards for analog test access and fault modeling. The two technical sessions that follow cover issues of implementing and debugging IEEE 1687 (IJTAG) networks; what works, what doesn’t, and how the IJTAG has been incorporated into DFT methodologies.