New Tools to Accelerate Silicon Debug and Bring-Up: a free webinar from Mentor and Teradyne
Don’t miss this free, one-hour, web-based seminar on December 6 from 11am-12pm PST if you want to learn how to overcome new chip bring-up issues and get your chips into production faster and more reliably. The session includes information on debug and characterization of digital and analog IP and a live demonstration.
Today’s semiconductor market landscape calls for increasingly complex designs for 5G wireless communications, autonomous driving, and artificial intelligence applications. The industry has been rapidly adopting IJTAG (IEEE 1687) for a plug-and-play style IP integration during design. IJTAG is proving to have a lot of value in managing the time and costs associated with the integration and test of increasingly large and complex designs. The benefits of using IJTAG are still emerging, as it allows for access and control of any embedded ‘instrument’ on a chip.
IJTAG also created an opportunity to greatly simplify the pattern bring-up and debug of silicon by allowing ATE and DFT software to connect, bridging the divide between DFT engineers and ATE engineers. Mentor and Teradyne have a system that allows DFT engineers and designers to access ATE remotely with incremental and light-weight communication through TCP.
The traditional flow involves converting test patterns to a tester-specific format and generating a test program that is executed by ATE. Each specific chip must have test patterns written by DFT engineers and then translated by test engineers to debug each scenario on each tester type. When any of these patterns fail, the ATE output is then translated into chip failure data and sent back to the DFT engineers to be processed by diagnosis tools. It is the DFT engineers, not the ATE test engineers, who play the main role in chip evaluation and debug. The result is many long iterations that delay time-to-market.
A new tool from Mentor eliminates this traditional flow by using an industry-standard interface to eliminate communication barriers between proprietary tester-specific software and DFT platforms. The result is to accelerate debug of IJTAG-compliant IP (aka, instruments), helping speed-up product ramps, and reducing time-to-market for products in 5G wireless communications, autonomous driving, and artificial intelligence. The first ATE to fully support the new Mentor interface is the Teradyne UltraFLEX ATE with Portbridge technology.
Tune into this webinar to learn about:
- Industry challenges for silicon debug and bring-up and how IJTAG (IEEE 1687) adoption is increasing
- Simplifying pattern bring-up and IJTAG debug
- How to reduce silicon bring-up time
- How to characterize an analog IP block enabled with IJTAG via a live demonstration
