Becki Watt
DFT for tile-based design

How to master DFT for tile-based designs

October 23, 2022

Hierarchical designs that are tile-based or abutment based physical blocks are predominant in today’s chips. Having no logic present at the chip-level calls for new approaches to testing these tile-based architectures. How a design for test (DFT) architecture can support tile-based designs is the focus of this presentation from U2U 2022.

By Tessent Solutions
2 MIN READ
A new way of measuring heterogeneous SoC performance

Explore a new way to measure heterogenous SoC performance at the Linley Fall Processor Conference

October 22, 2022

Join Siemens at the Linley Fall Processor Conference, the two-day event focusing on processors and IP cores used in embedded, communications, automotive, IoT,
and server designs.

By Tessent Solutions
2 MIN READ

Tessent at ISTFA 2022

October 21, 2022

Join Tessent at the 48th International Symposium for Testing and Failure Analysis, the premier event for the microelectronics failure analysis community.

By Tessent Solutions
< 1 MIN READ

Chip data joins the party with Tessent Host Services software

June 23, 2022

Siemens’ Tessent Embedded Analytics IP and software, Host Services software opens the lines of communication with your chip and brings SLS one step closer to reality.

By Tessent Solutions
2 MIN READ
Typical allocation of functional safety within an automotive SoC.

Webinar: Meet the Challenges of ISO 26262 with Tessent Test Solutions

May 4, 2022

Register Now! Tune in on June 9, 2022 at 11:00 am (pacific daylight time) to learn how to use Tessent…

By Tessent Solutions
< 1 MIN READ
D&R IP-SoC Day 2022 Silicon Valley

Siemens EDA talks cybersecurity at IP-SoC Silicon Valley

April 1, 2022

The Tessent group participated in the “unique event fully dedicated to IP and IP-based electronic systems,” D&R IP-SoC Silicon Valley…

By Tessent Solutions
< 1 MIN READ
Automated shared bus interface memory test

Webinar: Memory test using a shared bus Interface

March 31, 2022

The explosive growth in the use of memory content on SoCs calls for a new solution to effectively access the…

By Tessent Solutions
< 1 MIN READ

Introducing Tessent Streaming Scan Network

November 18, 2020

Slash test costs and reduce implementation effort for complex next-generation SoCs. IC engineering teams have seen a dramatic rise in…

By Tessent Solutions
2 MIN READ

Tessent’s ITC 2020 wrap-up

November 11, 2020

The International Test Conference carried on this year as a virtual event. It’s a difficult format to make work, but…

By Tessent Solutions
< 1 MIN READ