Reduce NPI profitability risks with a testing-based approach
Blog #4 in a 12-part series covering the Digital Twin Best Practices in Electronics Manufacturing mini-webinar series by Jay Gorajia
When it comes to profitability in the electronics manufacturing sector, we talk a lot about mitigating risks by performing design verification and discovering flaws during the board design phase. It’s clear that errors become costlier to fix as the project progresses. Can the same be said about errors in the test infrastructure of PCBs?
If you are an experienced PCB designer, you’ve surely been surprised by a net lacking test coverage, or by a test point that is blocked by an adjacent component, preventing access. Flaws such as these – which affect the manufacturability of your design – are usually identified by a test engineer during the Design for Test (DFT) analysis, which typically occurs late in the layout process, making the flaws costly to remediate. In addition, the analysis is manual and doesn’t scale well.
Wouldn’t it be more efficient if DFT could be analyzed by anyone in the design flow – as early as in the schematic capture or design phases – by putting advanced test strategy tools in the hands of designers? In the fourth session of our series of 12 mini-webinars on Implementing “Digital Twin” Best Practices From Design Through Manufacturing, we focus on on design verification from a testing point of view.
By improving the testability of PCBs early in the design process, we save money by avoiding scenarios like the one mentioned above, and drastically reduce the number of required re-spins. In this way, we can further implement the digital-twin strategy that “left-shifts” crucial processes and decisions, and help organizations get it right the first time.
In the webinar, we also introduce Valor® DFT – Siemens’ powerful and flexible design-for-test tool that can be leveraged by engineers across the PCB design flow.
Main takeaways from the session:
- How Valor DFT reduces risks to profitability by implementing test strategies early in the design process – reducing repair costs and eliminating scrap
- How to use Valor DFT to optimize test coverage of the board
- How Valor DFT uses DPMO (Defects Per Million Opportunities) ratings to determine the testing requirements of each component
- How to use Valor DFT check the alignment of the test strategy with the defect spectrum
