Full House – and this is no gamble!

SystemVerilog proved to be a “royal flush” of a reason for 100’s of people to gather together.

Leaving poker references behind, two SystemVerilog User Group meetings were held in India in November. The Cliff Cumming’s “fan club” came out in force at both the Noida and Bangalore locations. When I asked the SVUG members if they had read any Cliff’s online work, nearly everyone raised their hands.

Since nearly 100% of those who registered showed up at the Noida event, I was almost certain we would have the same full house in Bangalore. We did! Registration for the event had to close just 4 days after opening.

By the end of each of the events, Cliff was surrounded by user group members who kept asking him questions about SystemVerilog, looking for him to autograph the OVM Cookbook giveaway, shake his hand, and have a picture taken with him.

While Cliff shared tips on how designers can easily adopt SystemVerilog Assertions, I shared the fruit of the Accellera Verification Intellectual Property Technical Subcommittee (VIP-TSC) work. Accellera recently published the approved Verification Intellectual Property Recommended Practices guide.

SystemVerilog users also participated when they gave presentations the last half of the day and engaged in brisk and deep conversations on the application of SystemVerilog for design and verification. All the presentations have been cataloged and can be viewed by those who were unable to attend.

We look forward to the next SVUG meetings in India!