IEEE Standards Association Symposium on EDA Interoperability
Low Power Flow Kicks-off Symposium
In the world of electronic design automation, as an idea takes hold and works its way from thought to silicon, numerous tools are used by engineers and the like to help bring a good idea to product fruition. Standards play a key and important role to help move your user information from high-level concepts into the netlists can be realized in silicon. The IEEE Standards Association is holding a Symposium on EDA Interoperability to help members of the electronics/semiconductor design and verification community better understand the landscape of EDA and IP standards and the role they play to address interoperability.
Another key component are the programs and business relationships we foster to promote tool connectivity and interoperability among each other. The Questa users rely on the Questa Vanguard Partnership program so their trusted tool and technology partners have access to our verification technology to allow them to craft the leading edge design and verification flows with technology from numerous sources. If your users want you to connect with Questa, we invite them to explore the benefits of this program. Even better, join us at the IEEE SA Symposium on EDA Interoperability where can also discuss this in person – Register Here!
Event Details
Date: 24 October 2013
Time: 9:00 a.m. – 6:00 p.m. PT
Location: Techmart – 5201 Great America Parkway, Santa Clara, CA 95054-1125
Cost: Free!
Program: http://standards.ieee.org/events/edasymposium/program.html
One of the more pressing issues in design and verification today is address the issue of low power. The IEEE SA Symposium on EDA kicks-off the morning with its first session on “Interoperability Challenges: Power Management in Silicon.” The session will feature an opening presentation on the state of standardization by the Vice Chair of the IEEE P1801 Working Group (and Mentor Graphics Verification Architect) as well as two presentations from ARM on the use of the IEEE 1801 (UPF) standard.
| 11:00 a.m. – 12:00 p.m. | Session 1: Interoperability Challenges: Power Management in Silicon | |
| IEEE 1801 Low Power Format: Impact and Opportunities Erich Marschner, Vice Chair of IEEE P1801 Working Group, Verification Architect, Mentor Graphics |
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| Power Intent Constraints: Using IEEE1801 to improve the quality of soft IP Stuart Riches, Project Manager, ARM |
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| Power Intent Verification: Using IEEE1801 for the verification of ARM Cortex A53 processor Adnan Khan, Senior Engineer, ARM |
The event is sponsored by Mentor Graphics and Synopsys and we have made sure the symposium is free to attend. You just need to register. There are other great aspects to the event, not just the ability to have a conversation on the state of standards for low power design and verification in the morning. In fact, the end of the event will take a look at EDA 2020 and what is needed in the future. This will be a very interactive session that will open the conversation to all attendees. I can’t wait to learn what you have to share! See you at the Techmart on the 24th.
