DVCon Goes Global!
The ever popular Accellera Design & Verification Conference held annually in Silicon Valley is going global. Accellera System Initiative has expanded many of its SystemC user group events to be more inclusive of other Accellera and IEEE standards. In doing so, the local organizers of these events have moved to adopt the popular DVCon USA style to organize their events to include this large complement of standards. If you want to attend, participate or contribute to the events, follow the links as shared below.
Mentor Graphics is excited to participate and sponsor these user-led events with a keynote address, technical paper presentations and educational tutorials. We look forward to see you in September for DVCon India in Bangalore and in October for DVCon Europe in Munich.
DVCon Europe (14-15 October 2014 | Munich, Germany) will target the application of standardized languages, tools, and methodologies for the design and verification of electronic systems and integrated circuits. The two day event will feature tutorials on the first day and technical paper presentations and poster sessions on the second day. The DVCon Europe program list the details of the conference. It is collocated with the annual Forum on Design Languages (FDL), which runs from 14-16 October 2014 in case you want to extend your stay for an extra third day.
At DVCon Europe Mentor Graphics is collaborating with our industry peers and users on a tutorial titled Enabling Energy-Aware System Level Design with UPF-Based System Level Power Models. As power has become one of the major concerns in design equaling those of feature, function and performance, more advances are needed to address system power challenges. The tutorial will explore the use of IEEE Std. 1801™ (UPF) and how design and verification flows can best use it.
Mentor Graphics will also sponsor a tutorial titled Creating Portable Tests with a Graph-Based Test Specification. It will cover an overview of a graph-based test description language that raises the level of verification abstraction to address system level challenges. This technology is being used by many successful verification teams around the world today and it is the technology we have committed to help build a new standard upon in Accellera.
DVCon India (25-26 September 2014 | Bangalore, India) is the first year of the transition of the popular Indian SystemC User Group (ISCUG) meeting into an event that expands to cover topics that bring together all the stakeholder involved in design and verification of IP, SoC, ASIC, FPGA and system level solutions. The event is over two days with common sessions in the morning for keynote addresses. The attendees will then break into an ESL track and Design & Verification track for focused sessions.
Mentor Graphics will sponsor a tutorial session as well as host the keynote presentation by Mentor Graphics CEO, Dr. Walden C. Rhines. Dr. Rhines will review recent Wilson Research Group study results on the ongoing convergence of SoC design practices towards a common methodology, independent of specify tools being use. In this keynote, Dr. Rhines identifies the common attributes of SoC methodology that are emerging, and will highlight specific capability enablers for the further optimization of SoC design verification.
Registration for both events is now open and I hope you have time in your calendar to make it there. Both events will have an exhibition area where you can also catch up on recent updates to our products and discuss what you think should be added next. The Mentor Graphics team looks forward to meeting you there!
