See You at DVCon U.S. 2018!
We hope to see you at DVCon U.S. 2018. Mentor will showcase 17 papers and posters during the conference on topics covering CDC, coverage, debug, formal, low power, safety-critical, Portable Stimulus, UVM and more. To attend, you can register here. DVCon broadens its topic reach this year to include automotive system design and verification. In keeping with this call, Mentor has a tutorial that targets automotive product safety and embrace ISO 26262. Below are a few highlights and some details about where you will find the Mentor team.
Automotive Safety
If you have attended DVCon U.S. the past few years, you know the design and verification challenges that highly complex SoC’s have placed on traditional design have come into sharp focus. One of the driving factors for these challenges is the amount of electronics and embedded software the global transportation industry continues to add to their products. Systems and semiconductor makers must now consider the fault tolerance of their product offerings to this rapidly growing market. In the past, DVCon could focus on the RTL design and verification challenges alone. While good work was done to reduce the impact of errors in those systems, users had to tolerate personal computers that needed a reboot every now and then or a mobile device that could crash from time-to-time. But this cannot be tolerated in the emerging autonomous vehicles. Problems of the past that were an annoyance can be deadly when it comes to autonomous vehicles. Fortunately, the ISO 26262 standard defines the safety level of a design via specific safety goals, safety mechanisms, and fault metrics. Want to learn more? Need to learn more? Join us at the Mentor afternoon tutorial on Thursday to learn more and see how you can “stay out of the news.”
Tutorial: Thursday March 1 | 2:00pm – 5:30pm | Siskiyou Room
Title: How to Stay Out of the News with ISO 26262 Compliant Verification
Program Panel on Verification
Gone are the days when you could simply type in your RTL, simulate then go to silicon. Are you one who can remember that productivity was once measured by how fast you could type in your RTL code? Remember when that was the bottleneck to a completed design? Again, DVCon attendees know those days are well behind us. How do we solve the hardest verification problems now? The Wednesday afternoon panel offers an opportunity to gain some insight from those who are applying emulation, simulation, formal verification and FPGA prototyping tools with a mix of methodologies, along with new and emerging standards to make the world’s largest SoC’s a reality.
Panel: Wednesday February 28 | 1:30pm –2:30pm | Oak/Fir Room
Title: The Right Tool (or Tools) for the Toughest Verification Tasks
Wednesday Lunchtime Keynote
Mentor’s lunchtime keynotes are always popular. This year will be no exception. We will focus on validation, verification’s big brother. We know your insatiable need for speed feeds an ever increasing desire to achieve the highest productivity possible using simulation, emulation and prototyping. While we are feeding your body we will also feed your mind with ideas that will satisfy your craving for speed.
Lunch: Wednesday February 28 | 12:00pm – 1:15pm | Pine/Cedar Room
Title: Validation: Verification’s Big Brother – “I Wanna Go Fast”
Exhibition and Product Demos
There will be three days of exhibition and product demos. This is always a great place to meetup. And at the end of each day, a social hour is a great way to start the evening. If you want to discuss more about what you learned in sessions, tutorials, over lunch or during panel sessions, we are ready to share and show you more.
Exhibits: Mentor, A Siemens Business Booth #1101 (that’s decimal 1101; if in binary, is it your “lucky” number? – if Hex, it’s not a good grade!)
Monday February 26 | 5:00pm – 7:00pm
Tuesday February 27 | 2:30pm – 6:00pm
Wednesday February 28 | 2:30pm – 6:00pm
Low-Power SoC’s with Comprehensive Metrics-based Methodology
The past 10 years have seen consumer devices be the beneficiaries of reduced energy needs. With each reduction in the use of energy there is a nearly equal growth in design complexity to consume that reduction. To claim we are better now than 10 years ago and we don’t have to worry about this for the next 10 years falls short of the continued demands that come from nomadic IoT devices, 5G networking, consumer devices, automotive products, wearables and more. The constant progress of technology that presses the need for system energy considerations will not abate nor will the impacts from regulatory and governmental bodies yield to conservation. Want to learn more? Join us at the Mentor morning tutorial in Thursday to learn from the experts.
Tutorial: Thursday March 1 | 8:30am – 12:00pm | Siskiyou Room
Title: Comprehensive Metrics-Based Methodology to Achieve Low-Power System-on-Chips
Accellera Day Tutorials
DVCon begins with Accellera Day which will feature a morning and afternoon tutorial with a lunch break hosted by Accellera Systems Initiative. Accellera will educate us with updates to its popular UVM standard and introduce us to more of the details of its emerging Portable Stimulus Standard.
Portable Test and Stimulus: The Next Level of Verification Productivity is Here
Monday February 26 | 9:00am – 12:00pm | Oak/Fir Room
This in-depth technical tutorial will focus on a set of typical design use-cases from a variety of applications and show how to use the emerging Portable Test and Stimulus Standard to create an abstract model of your verification intent. The tutorial will then demonstrate how these models can be used to generate scenarios to be executed on the different platforms and environments used in your development process, and how the models can be reused and leveraged from project to project.
IEEE-Compatible UVM Reference Implementation and Verification Components
Monday February 26 | 2:00pm – 5:00pm | Oak/Fir Room
This tutorial will introduce engineers to the new reference implementation aligned with IEEE 1800.2 created by the Accellera UVM WG. The speakers will use the new reference implementation to describe the new features and changes relative to UVM 1.2. Engineers attending the tutorial will learn the steps they need to take to update their verification components to be IEEE-compatible. Code examples and interactive discussions with members of the Accellera UVM WG will help engineers gain the practical knowledge they need to adopt the IEEE 1800.2™ Standard for UVM.
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Quote:”Gone are the days when you could simply type in your RTL, simulate then go to silicon. Are you one who can remember that productivity was once measured by how fast you could type in your RTL code? Remember when that was the bottleneck to a completed design? Again, DVCon attendees know those days are well behind us. How do we solve the hardest verification problems now?”
And the problem goes back to being able to simulate Verilog was taken to mean that Verilog was a design language. And that then meant that schematics were simply taboo.
So the baby was thrown out with the bath water because the line titles had information that is key to verification. That is where the function and purpose of the net existed.
But since simulation was considered adequate for verification, the tools ignored the need to connect the network. But the designers improvised with spreadsheets, etc.
Meanwhile OOP and the dot.net framework evolved and the C#/Roslyn compiler will connect the blocks using Boolean expressions just like we used to manually create the schematic netlists.
I wonder how long it will take the EDA vendors to realize they dropped the ball………..