Emerging Commercial Acceptance of RISC-V

Over the past few years, you may have noted a growing number of articles in our Verification Horizons Publication that reference RISC-V.  RISC-V is an open instruction set architecture (ISA) to enable a new era of processor innovation through open standard collaboration.  Born out of research at UC Berkeley to support academic endeavors, it has grown to gain commercial interest and support as well.  The commercial interest is at the heart of our Questa Vanguard Partners exploring its use for production designs that they have shared in published articles.  The papers published to date include the following:

• June 2018
  • UVM-based Verification of a RISC-V Processor Core Using a Golden Predictor Model and a Configuration Layer
  • Creating SoC Integration Tests with Portable Stimulus and UVM Register Models
• March 2018
  • A Hierarchical and Configurable Strategy to Verify RISC-V based SoCs
• December 2017

  • How Static and Dynamic Failure Analysis Can Improve Productivity in the Assessment of Functional Safety
  • Step-by-step Tutorial for Connecting Questa® VIP into the Processor Verification Flow

• June 2017
  • Automation and Reuse in RISC-V Verification Flow

The transition from academic-only use to commercial use has been rather rapid.  While this has not diminished our deep and meaningful support of the market dominant CPU core suppliers, it has led Mentor Graphics and Siemens AG to join the RISC-V Foundation as many of you, our customers, have become members as well.  The formation of the RISC-V Foundation in 2015 has helped drive global attention to the open ISA and encourage the adoption and use in commercial products, which many of our Questa Vanguard Partners have been on the frontline of support for Mentor’s Questa simulator and Veloce emulator.  Our partners have taken academic research tools used for RISC-V development, such as Chisel, and brought RISC-V forward to current modern commercial practice using IEEE 1800™ SystemVerilog, IEEE 1800.2™ UVM and the Accellera Portable Stimulus standard to name a few.  This has made RISC-V popular for both the academic community and commercial concerns alike.

Upcoming Public Events

If you want to hear more from some of our partners on RISC-V, Codasip Ltd, Imperas Software Ltd and UltraSoC Technologies Ltd will present at DVCon Europe a tutorial on RISC-V Design and Verification on Wednesday, October 24, 2018 in Munich, Germany.  The tutorial will explore the issues and challenges of SoC designers adopting RISC-V from the perspectives of IP Cores, software tools, virtual platforms and on-chip debug analytics for complex multi-core and heterogeneous many-core designs.

The RISC-V Foundation holds its annual Summit to bring together the academic community, commercial supporters and backers along with a growing number of ecosystem participants.  In the past, these events were sponsored by corporate benefactors at their cooperate locations.  The number of participants has led to the group to move to the Santa Clara Convention Center this year.  The RISC-V Summit will be held December 3 – 6, 2018.

In addition to these two event venues, the RISC-V Foundation maintains a list of events around the world that may interest you.  Check them out!