Don’t Miss the Upcoming DVClub Austin Event!
If you have a passion for design and verification, then I highly recommend that you check out the DVClub. The DVClub’s charter is to provide local education and networking events for the semiconductor verification and design community in North America, and regularly holds events across North America including – San Jose, Austin, Boston, Portland, Toronto, RTP, and Fort Collins.
The next event occurs on September 27, 2019 at 11:30 AM in Austin Texas at the Norris Conference Center, and includes a catered lunch and networking. At this event there are three fantastic technical speakers lined up: James Gorman (a System Lead and architect on the CPU Subsystem team at Ericsson ASIC Design Center in Austin), Glenn Canto (a builder of virtual platforms at Ericsson), and Rich Edelman (a Verification Technologist at Mentor, a Siemens Business).
The first invited talk by James Gorman is titled “What is 5G?” This is a timely topic. Particularly since it seems that everyone is talking about 5G, but not everyone knows what it really means. In James’ talk he will introduce key technical features 5G and what it means for users. Built on latest technologies, hear how Ericsson’s architecture brings new semiconductor design and verification challenges and about how Ericsson has addressed them.
The second invited talk by Glenn Canto is titled “Effective Reuse through Virtual Platforms at Ericsson.” Virtual platforms are frequently used only as a stopgap solution for facilitating pre-silicon software development, but there is often overlooked potential for reuse in verification environments. Similarly, by providing quality tools to their software developers, the virtual platform becomes reusable post-silicon. In this talk, Glenn shares his experience with virtual platforms, and their integration with Ericsson’s hardware verification environment and dynamic analysis tools supporting software development.
Finally, the famous Rich Edelman will give a talk titled “UVM – Where Are We? Is it Safe?” As you know, UVM has been around for years, and gone through many versions, and is now an IEEE standard. But the question remains – Where Are We? Join Rich for a quick flash through verification techniques over the years from Verilog “input/expected output” to PLI to vera and e to SV and DPI to UVM. Rich will spend time on a variety of UVM functionalities, including UVM Config, UVM Transaction Recording, UVM Registers and the Out-of-Order transaction issue. At each point he’ll ask “Where are we”? Do we need changes? Do we just need to make the code “Safe”? In this invited talk Rich will share his expertise about UVM past, present and future.
For more information and registration details, check out the DVClub website. I hope to see you there!
