Bringing Some of DVConUS to You
As always, the Mentor team was a substantial part of the program at this year’s DVCon US. Unfortunately, due to the COVID-19 virus, the program was shortened since not all presenters nor registrants were able to attend. However, for those of you unable to attend, we are pleased to share with you some of the great technical content that Mentor folks contributed to the conference. All of these papers and presentations can be found at Verification Academy (which will require a free registration if you are not already a member).
Harry Foster was invited to fill in part of the abbreviated program by sharing some results and additional thoughts from a recent industry-wide survey he oversaw on “FPGA Verification Maturity: A Quantitative Analysis.”
You’ll also see our great Workshop presentation, “Mind the Gap(s): Closing and Creating Gaps Between Design and Verification.”
Rich Edelman and Chris Spear, both long-time colleagues and friends, won 2nd place for the Stu Sutherland Best Paper Award with “UVM – Stop Hitting Your Brother Coding Guidelines.”
Our stellar Formal Verification team of Mark Eslinger, Jeremy Levitt and Joe Hupcey won 2nd place for the Best Poster Award with “Deadlock Verification For Dummies – The Easy Way Using SVA and Formal.”
Other Mentor papers of note:
- Are You Safe Yet? Safety Mechanism Insertion and Validation
- Did Power Management Break My CDC Logic? An Integrated Approach to Power Domain and Clock-Domain Crossing Verification
- How UPF 3.1 Reduces the Complexities of Reusing Power Aware Macros
- Scalable Reset Domain Crossing Verification Using Hierarchical Data Model
- SystemVerilog Constraints: Appreciating What You Forgot in School to Get Better Results
- UPF 1.0, UPF 2.0, UPF 2.1, UPF 3.0, and now UPF 3.1: The big Q Which is the Right Standard for My Design?
- Systematic Methodology to Solve Reset Challenges in Automotive SoCs
