Siemens EDA @DVConUS 2022

DVConUS is coming up, beginning on February 28, 2022. The conference will be virtual again for 2022, but I’d like to give you two great reasons to attend this year. The first is that the conference will have a new virtual exhibit floor (using gather.town), which will give attendees plenty of opportunities to interact virtually with representatives of Siemens EDA (including yours truly) and other vendors and colleagues. The second is that, as always, Siemens EDA will have a ton of content in the DVCon program for you to enjoy. Here’s a breakdown (all times, PST) of everything that we’re doing at DVConUS this year:

• Monday, February 28, 2022
  • 1pm-2pm [Sponsored Workshop] – Estimating Power Dissipation of End-User Application on RTL (Kevin Hotaling, Magdy El-Moursy):
    A methodology is presented to estimate the power dissipation of an end-user application on the Register Transfer Level (RTL) model of the target SoC platform.
• Tuesday, March 1, 2022
  • 9am-10:30am [Portable Stimulus Standard (PSS)] – Co-Developing IP and SoC Bring-up Firmware with PSS (Matthew Ballance):
    This paper proposes an Accellera Portable Test and Stimulus (PSS) -enabled flow for co-developing and co-verifying design IP and firmware.
  • 10:30am-12:00pm [Poster Presentations]
    • Modeling Analog Devices using SV-RNM (Mariam Maurice):
      This poster discusses new ways of modeling analog devices in SystemVerilog using Real-Number Modeling (RNM), including debug and visualization techniques for mixed-signal designs.
    • Confidently Sign-off any Low-Power Designs without Consequences (Madhur Bhargava, Jitesh Bonshal, Progyna Khondkar):
      This poster uses case studies to provide an in-depth analysis of various low-power design issues and demonstrate how these issues can be either avoided or solved during RTL bring-up.
    • Avoiding Confounding Configurations: An RDC Methodology for Configurable Designs (Eamonn Quigley, Jonathan Niven, Arm; Kurt Takara, Christopher Giles, Siemens)
    • Why not “Connect” using UVM Connect: Mixed-Language communication got easier with UVMC (Vishal Baskar):
      This poster shows how UVM Connect can be used to verify high-level SystemC models in your SystemVerilog UVM environment and reuse the verification infrastructure as you refine the models into RTL.
  • 3pm-5pm [Formal Verification 1] – How to Avoid the Pitfalls of Mixing Formal and Simulation Coverage (Mark Eslinger, Joe Hupcey III, Nicolae Tusinschi):
    This paper will review what “coverage” means in the context of different tools and discuss how to merge them together in a manner that accurately reports status and expected behaviors.
• Wednesday, March 2, 2022
  • 3pm-5pm [UVM: Knobs and Sequences] – What Does the Sequence Say? Powering Productivity with Polymorphism (Rich Edelman):
    On the one hand, a sequence is simply a list of instructions, but on the other hand, how those instructions are built or how they are used with other instructions can improve the test. This paper will demonstrate such improvements.
  • 3pm-5pm [Low Power and UPF] – Path-based UPF Strategies Optimally Manage Power on your Designs (Progyna Khondkar):
    This paper uses real design examples to simplify the adoption of a standard path-based UPF approach using isolation, level-shifter, and repeater strategies.
  • 3pm-5pm [Prototyping] – Evaluating the feasibility of a RISC-V core for real-time applications using a virtual prototype (Juan Santana, Gabriel Pachiana, Thomas Markwirth, Christoph Sohrmann, Fraunhofer IIS/EAS; Bernhard Fischer, Martin Matschnig, Siemens AG):
    This paper proposes a HW/SW co-verification methodology to evaluate the feasibility of an MCU core replacement with a RISC-V core based on a virtual prototype. This methodology links the VP development process with the requirements management process to re-use the test cases, thereby saving time and cost for the redesign process.
• Thursday, March 3, 2022
  • 9am-11am [Sponsored Tutorial] – The Best Verification Strategy You’ve Never Heard Of (Harry Foster, David Aerne, Kurt Takara, Amir Attarha):
    This tutorial will explore two approaches to minimizing hardware bugs. The first will be to apply various static and formal analysis techniques to the design to eliminate bugs before simulation starts. We will walk through several approaches to bug avoidance, such as linting, automatic formal applications, and other static analysis techniques, and see how this pro-active strategy is a clear win compared to bug detection and correction as you may be used to. The second will be to design and verify at a higher level of abstraction in fewer lines of code, thus minimizing the number of bugs introduced, and use high-level synthesis to step through a design and verification flow based on reuse of verification and correct-by-construction RTL executed on a unified hardware-assisted verification system, taking you all the way from hybrid virtual platforms to emulation and FPGA-based prototyping, and achieving your quality goals in one seamless environment.
  • 11:30am-12:30pm [Sponsored Workshop] – System Verification with MatchLib (Russell Klein):
    MatchLib is a SystemC-based throughput-accurate communication package developed by Nvidia and available as open-source that can be used to model common buses like AXI, enabling much faster simulation of a design while retaining throughput accuracy. This workshop will walk through examples using the RISC-V Rocket core, a MatchLib modeled interconnect, and a simple inferencing application that will be run in simulations both as an abstract model in SystemC and as RTL (created from the SystemC model using High-Level Synthesis) to explore the different verification objectives that can be achieved at each stage of the design process.

That’s quite a list! And remember that these technical sessions are only part of the program. There will also be opportunities to interact with many of us at the virtual Siemens EDA booth. We hope to “see” you at DVConUS.