Thought Leadership

Epilogue: The 2022 Wilson Research Group Functional Verification Study

This is the last in a sequence of blogs that presents the findings from our new 2022 Wilson Research Group Functional Verification Study. I opened this blog series with a Prologue posting that provided an overview of this year’s study. I think it is only fitting that I end this series with an Epilogue posting that summarizes some of this year’s key findings.

Study Value

We continue to receive a remarkable amount of positive feedback from our studies, and I think the following quote sums up nicely the general sentiment:  

“I believe that the industry data that Siemens EDA gathers is very valuable to our organization.  The data enables us to identify and gain insight into trends related to FPGA and ASIC design, including tools and methodologies. This enables us to align our organization strategies to take advantage of the solutions being developed by commercial industry. This results in cost savings and faster execution of our designs.”

Executive, Mil-Aero Industry

2022 Study Summary and Key Findings

The FPGA market continues to go through a similar complexity curve that the IC/ASIC market experienced in the early and mid-2000 timeframe. In particular with the emergence of SoC-class designs. Like the IC/ASIC market during that timeframe, the FPGA market today has been forced to mature its functional verification processes. This is easily measured in our study by examining the increased adoption of functional verification technology, as well as the growth in verification engineers as FPGA team members.

Perhaps the most disturbing finding from this year’s study relates to the number of FPGA projects with nontrivial bug escapes into production. We did find an interesting correlation between the improvement of reduced functional flaws contributing to non-trivial bug escapes, as discussed in my previous blog, and the maturing of FPGA projects’ functional verification processes.

For the IC/ASIC market, and probably the biggest surprise we found in the 2022 data was the decline in first-silicon success. In fact, achieving first silicon success was the lowest measured value that we have seen in the past 20 years. Also for the IC/ASIC market, we continued to see a significant amount of flaws attributed to analog issues. One explanation to this issue is the recent increase integration of analog across the board in terms of various sized designs, and this is contributing to an increase in analog issues.

We have various ideas for deeper analysis we plan to perform on this year’s data. And we plan additional blogs in the future revealing some of these findings.

Quick links to the 2022 Wilson Research Group Study results

Harry Foster

Harry Foster is Chief Scientist Verification for the Design Verification Technology Division of Mentor, A Siemens Business; and is the Co-Founder and Executive Editor for the Verification Academy. In addition, Harry is serving as the 2021 Design Automation Conference General Chair. He holds multiple patents in verification and has co-authored six books on verification. Harry was the 2006 recipient of the Accellera Technical Excellence Award for his contributions to developing industry standards, and was the original creator of the Accellera Open Verification Library (OVL) standard.

More from this author

Leave a Reply

This article first appeared on the Siemens Digital Industries Software blog at https://blogs.stage.sw.siemens.com/verificationhorizons/2023/01/23/epilogue-the-2022-wilson-research-group-functional-verification-study/